AD6600ASTZ Analog Devices Inc, AD6600ASTZ Datasheet - Page 17

• Manufacturer Part Number: AD6600ASTZ
• Description: ADC Single 20MSPS 11-Bit Parallel 44-Pin LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD6600ASTZ

• Package: 44LQFP
• Resolution: 11 Bit
• Sampling Rate: 20000 KSPS
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Digital Interface Type: Parallel
• Input Type: Voltage
• Signal To Noise Ratio: 59(Typ) dB
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar
• Number Of Bits: 11
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 976mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mode
Dual: A/B
Single: A
Single: B
Not Valid
A_SEL and B_SEL are not logic inputs and should be tied
directly to ground or analog VCC (5 V analog).
In dual channel mode, the AB_OUT signal indicates which
input is currently available on the digital output. When the
AB_OUT is 1, the digital output is the digitized version of
Channel A. Likewise, when AB_OUT is 0, the Channel B is
available on the digital output (Table III).
A_SEL and B_SEL = 1
D[10:0], RSSI[2:0]
AB_OUT
Data Output Stage
The output stage provides data in the form of mantissa, D[10:0],
and exponent, RSSI[2:0], where D[10:0] represents the output
of the 11-bit ADC coded as two’s complement, and RSSI[2:0]
represents the gain-range setting coded in offset binary. Table
IV shows the nominal gain-ranges for a nominal 2 V p-p differ-
ential full-scale input. Keep in mind that the actual full-scale
input voltage and power will vary with input frequency.
Differential
Analog Input Voltage
(V p-p)
0.5 < V
0.25 < V
0.125 < V
0.0625 < V
0.03125 < V
V
The digital processing chip which follows the AD6600 can com-
bine the 11 bits of two’s complement data with the 3 RSSI bits
to form a 16-bit equivalent output word. Table V explains how
the RSSI data can be interpreted when using a PLD or ASIC.
Basically, the circuit performs right shifts of the data depending
on the RSSI word. This can also be performed in software using
the following pseudo code fragment:
The result of the shifted data is a 16-bit fixed-point word that
can be used as any normal 16-bit word.
IN
r0 = dm (rssi);
r2 = 5;
r0 = r2–r0;
r1 = dm (adc); (11 bits, MSB justified into DSP word)
rshift r1, r0; (arithmetic shift to extend the sign bit)
< 0.03125
Table III. AB_OUT for Dual Channel Operation
IN
IN
Table II. Selecting AD6600 Operating Mode
IN
< 0.5
IN
< 0.25
IN
Table IV. Interpreting the RSSI Bits
< 0.125
A_SEL
1
1
0
0
< 0.0625
B_SEL
1
0
1
0
Output Data vs. Encode Clock
n
A
1
Binary
101
100
011
010
001
000
RSSI [2:0]
Output vs. Encode Clock
n
A
A
B
–
Decimal
Equiv.
5
4
3
2
1
0
n+1
B
0
n+1
B
A
B
–
n+2
A
1
Attenuation
or Gain (dB)
–12
–6
0
+6
+12
+18
n+2
A
A
B
–
n+3
B
A
B
–
n+3
B
0
RSSI
101
100
011
010
001
000
When mated with the AD6620, Digital Receive Processor Chip,
the AD6600 floating point data (mantissa + exponent) is automati-
cally converted to 16-bit two’s complement format by the AD6620.
APPLYING THE AD6600
Encoding the AD6600
The AD6600 encode signal must be a high quality, extremely
low phase noise source to prevent degradation of performance.
Digitizing high frequency signals (IF range 70 MHz–250 MHz)
places a premium on encode clock phase noise. SNR perfor-
mance can easily degrade by 3 dB–4 dB with 70 MHz input
signals when using a high-jitter clock source. At higher IFs (up
to 250 MHz), and with high-jitter clock sources, the higher
slew rates of the input signals reduce performance even further.
See AN-501, Aperture Uncertainty and ADC System Performance
for complete details.
For optimum performance, the AD6600 must be clocked differ-
entially. The encode signal is usually ac-coupled into the ENC
and ENC pins via a transformer or capacitors. These pins are
biased internally and require no additional bias.
Figure 18 shows one preferred method for clocking the AD6600.
The sine source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD6600 to approximately 0.8 V p-p differential. This
helps prevent the larger voltage swings of the clock from feeding
through to other portions of the AD6600, and limits the noise
presented to the encode inputs. A crystal clock oscillator can
also be used to drive the RF transformer if an appropriate
limiting resistor (typically 100 Ω) is placed in the series with
the primary.
11-Bit Word
DATA
DATA
DATA
DATA
DATA
DATA
Table V. 16-Bit, Fixed-Point Data Format
SOURCE
SINE
100
T1–1T
16-Bit Data
Format
DATA× 32
DATA× 16
DATA× 8
DATA× 4
DATA× 2
DATA× 1
5082–2810
DIODES
ENCODE
ENCODE
AD6600
Corresponds to a
Shift Right of
5
4
3
2
1
0
AD6600