89HPES5T5ZBBC Integrated Device Technology (Idt), 89HPES5T5ZBBC Datasheet - Page 2

• Manufacturer Part Number: 89HPES5T5ZBBC
• Description: PCI Express Switch 196-Pin CABGA Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89HPES5T5ZBBC

• Package: 196CABGA
• Operating Temperature: 0 to 70 °C

Product Description
throughput, low latency, and simple board layout with a minimum number of board layers. It provides 2.5 GBps (20 Gbps) of aggregated, full-duplex
switching capacity through 5 integrated serial lanes, using proven and robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in both direc-
tions and is fully compliant with PCI Express Base specification revision 1.1.
tion layers in compliance with PCI Express Base specification Revision 1.1. The PES5T5 can operate either as a store and forward or cut-through
switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated
resource management to allow efficient switching for applications requiring additional narrow port connectivity.
SMBus Interface
configuration register in the device to be read or written by an external agent. The master interface allows the default configuration register values of
the PES5T5 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an
external Hot-Plug I/O expander.
the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master interface, these
address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up
on negation of PERSTN by sampling the corresponding address pins. When the pins are sampled, the resulting address is assigned as shown in
Table 1.
IDT 89PES5T5 Data Sheet
Utilizing standard PCI Express interconnect, the PES5T5 provides the most efficient I/O connectivity solution for applications requiring high
The PES5T5 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-
The PES5T5 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES5T5, allowing every
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In
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11 General Purpose Input/Output Pins
Packaged in a 15mm x 15mm 196-ball BGA with 1mm ball spacing
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Figure 2 I/O Expansion Application
x1
LOM
GE
Processor
x1
LOM
GE
2 of 28
Bridge
PES5T5
North
Bridge
South
Processor
x1
x1
GE
x1
Memory
1394
Memory
Memory
Memory
May 7, 2009