89HPES5T5ZBBC Integrated Device Technology (Idt), 89HPES5T5ZBBC Datasheet - Page 3

• Manufacturer Part Number: 89HPES5T5ZBBC
• Description: PCI Express Switch 196-Pin CABGA Tray
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89HPES5T5ZBBC

• Package: 196CABGA
• Operating Temperature: 0 to 70 °C

3(a), the master and slave SMBuses are tied together and the PES5T5 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES5T5 registers supports SMBus arbitration. In some systems, this SMBus master
interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support
these systems, the PES5T5 may be configured to operate in a split configuration as shown in Figure 3(b).
The PES5T5 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the
serial EEPROM.
Hot-Plug Interface
an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-
ever the state of a Hot-Plug output needs to be modified, the PES5T5 generates an SMBus transaction to the I/O expander with the new value of all of
the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate
function of GPIO) of the PES5T5. In response to an I/O expander interrupt, the PES5T5 generates an SMBus transaction to read the state of all of the
Hot-Plug inputs from the I/O expander.
IDT 89PES5T5 Data Sheet
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES5T5 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES5T5 utilizes
(a) Unified Configuration and Management Bus
PES5T5
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
Bit
Table 1 Master and Slave SMBus Address Assignment
1
2
3
4
5
6
7
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
...
Devices
SMBus
Other
SSMBADDR[1]
SSMBADDR[2]
SSMBADDR[3]
SSMBADDR[5]
Address
SMBus
Slave
3 of 28
0
1
1
(b) Split Configuration and Management Buses
PES5T5
MSMBADDR[1]
MSMBADDR[2]
MSMBADDR[3]
MSMBADDR[4]
Address
Master
SMBus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
1
0
1
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
May 7, 2009