9DB206CLLF Integrated Device Technology (Idt), 9DB206CLLF Datasheet

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9DB206CLLF

Manufacturer Part Number
9DB206CLLF
Description
PCI Express Jitter Attenuator 28-Pin TSSOP
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 9DB206CLLF

Package
28TSSOP
Operating Temperature
0 to 70 °C
B
PCI EXPRESS JITTER ATTENUATOR
IDT
G
synthesizer. In these systems, a jitter-attenuating device may be
necessary in order to reduce high frequency random and
deterministic jitter components from the PLL synthesizer and from
the system board. The ICS9DB206 has two PLL bandwidth modes.
In low bandwidth mode, the PLL loop bandwidth is 500kHz. This
setting offers the best jitter attenuation and is still high enough to
pass a triangular input spread spectrum profile. In high bandwidth
mode, the PLL bandwidth is at 1MHz and allows the PLL to pass
more spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5
multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropriate
frequency select pins (FS0:1). Output PCIEX0 will always run at
the reference clock frequency (usually 100MHz) in desktop PC
PCI Express Applications.
nOE0
nOE1
nCLK
HiPerClockS™
IREF
CLK
IC S
FS0
FS1
LOCK
ENERAL
/ ICS
PCI EXPRESS JITTER ATTENUATOR
D
The ICS9DB206 is a high perfromance 1-to-6
Differential-to-HCSL Jitter Attenuator designed for
use in PCI Express™ systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, high phase noise PLL frequency
IAGRAM
+
Detector
-
D
Phase
ESCRIPTION
Internal Feedback
Current
Set
÷5
Loop
Filter
1 HiZ
0 Enabled
1 HiZ
0 Enabled
VCO
0 ÷4
1 ÷5
0 ÷5
1 ÷4
÷5
1
Features
Six 0.7V current mode differential HCSL output pairs
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Input frequency range: 90MHz - 140MHz
VCO range: 450MHz - 700MHz
Output skew: 110ps (maximum)
Cycle-to-Cycle jitter: 110ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
Industrial temperature information available upon request
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
P
5.3mm x 10.2mm x 1.75mm body package
4.4mm x 9.7mm x 0.92mm body package
IN
A
PCIEXC0
PCIEXC1
PCIEXC2
PCIEXT0
PCIEXT1
PCIEXT2
PLL_BW
ICS9DB206CL REV B JULY 14, 2006
28-Lead TSSOP, 173-MIL
28-Lead, 209-MIL SSOP
SSIGNMENT
nOE0
nCLK
GND
CLK
FS0
V
V
DD
DD
ICS9DB206
ICS9DB206
F Package
L Package
Top View
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ICS9DB206
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
GND
IREF
FS1
PCIEXT5
PCIEXC5
V
GND
PCIEXT4
PCIEXC4
PCIEXT3
PCIEXC3
V
nOE1
DDA
DD
DD

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9DB206CLLF Summary of contents

Page 1

PCI EXPRESS JITTER ATTENUATOR G D ENERAL ESCRIPTION The ICS9DB206 is a high perfromance 1-to Differential-to-HCSL Jitter Attenuator designed for use in PCI Express™ systems. In some PCI Express HiPerClockS™ systems, such as those found in desktop PCs, ...

Page 2

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR ABLE IN ESCRIPTIONS ...

Page 3

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance Lead TSSOP 49.8°C/W (0 lfpm) 28 Lead SSOP ...

Page 4

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR T 4D. HCSL DC C ABLE HARACTERISTICS ...

Page 5

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k The illustrated phase noise plot was taken using a low phase noise signal generator, ...

Page 6

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR P ARAMETER 3.3V±5% V DD, V DDA HCSL GND 0V 3.3V HCSL UTPUT OAD EST PCIEXC0:5x PCIEXT0:5x PCIEXC0:5y PCIEXT0:5y t sk( UTPUT KEW 80% Clock 20% Outputs t ...

Page 7

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR OWER UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB206 provides separate power supplies to isolate any high switching ...

Page 8

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show interface ...

Page 9

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR S E CHEMATIC XAMPLE The schematic below illustrates two different terminations. Both are reliable and adequate. The PCI Express termination is recommended for all PCI Express application. The optional VCC R19 33 ...

Page 10

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR T 6A ABLE VS IR LOW ABLE OR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...

Page 11

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR ACKAGE UTLINE UFFIX FOR T 7A ABLE ACKAGE IMENSIONS ...

Page 12

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR ABLE RDERING NFORMATION ...

Page 13

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR ...

Page 14

ICS9DB206 PCI EXPRESS JITTER ATTENUATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 ...

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