9DB206CLLF Integrated Device Technology (Idt), 9DB206CLLF Datasheet - Page 7

• Manufacturer Part Number: 9DB206CLLF
• Description: PCI Express Jitter Attenuator 28-Pin TSSOP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 9DB206CLLF

• Package: 28TSSOP
• Operating Temperature: 0 to 70 °C

W
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
IDT
P
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB206 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illus-
trates how a 24
capacitor should be connected to each V
tor can also be replaced by a ferrite bead.
OWER
ICS9DB206
PCI EXPRESS JITTER ATTENUATOR
IRING THE
™
/ ICS
™
S
PCI EXPRESS JITTER ATTENUATOR
UPPLY
D
IFFERENTIAL
resistor along with a 10 F and a .01 F bypass
F
ILTERING
DD
and V
I
NPUT TO
T
ECHNIQUES
DDA
F
IGURE
should be individually con-
Single Ended Clock Input
A
DDA
CCEPT
2. S
A
pin. The 10
PPLICATION
INGLE
S
INGLE
E
C1
0.1u
NDED
V_REF
DD
resis-
/2 is
E
NDED
S
IGNAL
7
I
L
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
D
1K
EVELS
R1
1K
R2
RIVING
VDD
CLK
nCLK
D
IFFERENTIAL
F
IGURE
1. P
V
I
V
DDA
NPUT
DD
OWER
ICS9DB206CL REV B JULY 14, 2006
DD
.01 F
S
= 3.3V, V_REF should be 1.25V
.01 F
UPPLY
3.3V
F
24
10 F
ILTERING