MT48LC8M16A2B4-75:G TR Micron Technology Inc, MT48LC8M16A2B4-75:G TR Datasheet - Page 31

• Manufacturer Part Number: MT48LC8M16A2B4-75:G TR
• Description: DRAM Chip SDRAM 128M-Bit 8Mx16 3.3V 54-Pin VFBGA T/R
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC8M16A2B4-75:G TR

• Density: 128 Mb
• Maximum Clock Rate: 133 MHz
• Package: 54VFBGA
• Address Bus Width: 14 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 6|5.4 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 54-VFBGA
• Organization: 8Mx16
• Address Bus: 14b
• Access Time (max): 6/5.4ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 18:
WRITEs
PDF: 09005aef8091e66d/Source: 09005aef8091e625
128MSDRAM_2.fm - Rev. N 1/09 EN
Terminating a READ Burst
Notes:
COMMAND
COMMAND
1. DQM is LOW.
WRITE bursts are initiated with a WRITE command, as shown in Figure 19 on page 32.
auto precharge either is enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored (see Figure 20 on page 32). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
The starting column and bank addresses are provided with the WRITE command, and
ADDRESS
ADDRESS
CLK
CLK
DQ
DQ
BANK,
T0
COL n
T0
BANK,
COL n
READ
READ
CL = 2
T1
T1
NOP
NOP
CL = 3
31
T2
T2
NOP
NOP
D
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
n + 1
D
D
OUT
OUT
n
TRANSITIONING DATA
TERMIN ATE
TERMIN ATE
T4
BURST
BURST
T4
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
128Mb: x4, x8, x16 SDRAM
X = 2 cycles
T5
T5
NOP
NOP
n + 3
n + 2
D
D
OUT
OUT
©1999 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
n + 3
D
OUT
DON’T CARE
Operations
T7
NOP