XC3S700AN-4FG484C Xilinx Inc, XC3S700AN-4FG484C Datasheet - Page 97

• Manufacturer Part Number: XC3S700AN-4FG484C
• Description: FPGA Spartan®-3AN Family 700K Gates 13248 Cells 667MHz 90nm Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc

Specifications of XC3S700AN-4FG484C

• Package: 484FBGA
• Family Name: Spartan®-3AN
• Device Logic Units: 13248
• Device System Gates: 700000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 372
• Ram Bits: 368640

Table 76: Spartan-3AN FGG400 Pinout (Cont’d)
User I/Os by Bank
Table 77
The AWAKE pin is counted as a dual-purpose I/O.
Table 77: User I/Os Per Bank for the XC3S400AN in the FGG400 Package
Footprint Migration Differences
The XC3S400AN is the only Spartan-3AN FPGA offered in the FGG400 package.
The XC3S400AN FPGA is pin compatible with the Spartan-3A XC3S400A FPGA in the FG(G)400 package, although the
Spartan-3A FPGA requires an external configuration source.
DS557 (v4.1) April 1, 2011
Product Specification
Top
Right
Bottom
Left
VCCAUX TMS
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Bank
Package
Edge
Total
indicates how the 311 available user-I/O pins are distributed between the four I/O banks on the FGG400 package.
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
I/O Bank
Pin Name
0
1
2
3
Maximum I/Os
311
77
79
76
79
FGG400
Ball
N20
M11
N10
A13
E16
K13
K11
J10
J12
L10
L12
H1
M9
E4
T5
Y8
K9
L8
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
JTAG
Type
155
I/O
50
21
35
49
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INPUT
12
12
16
46
6
All Possible I/O Pins by Type
Spartan-3AN FPGA Family: Pinout Descriptions
DUAL
30
21
52
1
0
VREF
26
6
8
6
6
CLK
32
8
8
8
8
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