TEA5764UK/N2,027 NXP Semiconductors, TEA5764UK/N2,027 Datasheet - Page 21

• Manufacturer Part Number: TEA5764UK/N2,027
• Description: Tuners FM RADIO WITH RDS
• Manufacturer: NXP Semiconductors

Specifications of TEA5764UK/N2,027

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278071027 TEA5764UK-G

Philips Semiconductors
TEA5764UK_2
Product data sheet
9.1.4.4 IF frequency flag
9.1.4.5 RSSI threshold flag
If bit LSYNCMSK is 0 and synchronization is lost, the ASIC automatically starts a new
synchronization search. It will not generate a hardware interrupt. The microprocessor can
wait until the RDS decoder is synchronized again, this will be indicated by the DAVFLG
and the SYNC status bit (this requires bit DAVMSK being set).
Bit LSYNCFL is reset by a read of the INTMSK byte1R.
Bit LSYNCMSK is not reset by a read of byte INTMSK, it must be set or reset by the
microprocessor. Resetting it automatically would change the status of the ASIC and cause
an automatic synchronization search as described above.
How the synchronization is defined is explained in brief in
During an automatic frequency search, preset or AF update, the FM part of the
TEA5764UK performs a check of the received IF frequency as a measure of the level of
interference in the channel received. If an incorrect IF frequency is received, it indicates
the presence of either strong interferers or tuning to an image which sets bit IFFLAG in the
INTFLAG register. Also a preset to a channel with no signal will result in a wrong IF count
value and hence the setting of bit IFFLAG.
When a search, preset or AF update is finished, bit FRRFLAG will be set to indicate this
and will generate an interrupt. The microprocessor can now read the outcome of the
registers which will contain the IF count value and the IFFLAG status of the channel it is
tuned to. In the case of an AF update, the IF count value of the alternative frequency will
be in the registers and also when it jumps back, because it will then not start a new IF
count.
15 ms after the tuning algorithm has completed the IF counter will start a new count. So
30.6 ms after a failed AF update the IF count result will be equal again to that of the
channel from where the jump was initiated.
15 ms after the FRRFLAG has been set the IF counter will start to run continuously on the
tuned frequency and if the conditions for correct frequency are not met then this sets bit
IFFLAG in the interrupt register. When bit IFMSK is set this will also cause an interrupt.
Bit IFFLAG is cleared by a read of byte1R, or by starting the tuning algorithm.
The voltage level reflects the field strength received by the antenna. The voltage level is
analog to digital converted to a 4-bit value and output via the I
can be compared to a threshold level set by the SSL bits in
Table
The ADC level (which converts the analog value to digital) can be triggered to convert in
either of two ways:
1. During a tuning step, a search, a preset or an AF update, it is triggered by these
algorithms and compares the level with the threshold set by bits SSL[1:0]. Bit
LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0]
(see
is set.
26.
Table
19). The hardware interrupt is only generated if the corresponding mask bit
Rev. 02 — 9 August 2005
Section
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table 19
2
C-bus, this 4-bit level value
TEA5764UK
10.
or the LH bits in
FM radio + RDS
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