TEA5764UK/N2,027 NXP Semiconductors, TEA5764UK/N2,027 Datasheet - Page 22

• Manufacturer Part Number: TEA5764UK/N2,027
• Description: Tuners FM RADIO WITH RDS
• Manufacturer: NXP Semiconductors

Specifications of TEA5764UK/N2,027

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935278071027 TEA5764UK-G

Philips Semiconductors
TEA5764UK_2
Product data sheet
9.1.4.6 Pause detection flag
Bit LEVFLAG is cleared by a read of the INTMSK byte1R, or by starting the tuning
algorithm.
The pause detector monitors the amplitude of the audio signal and starts counting if it
drops below the reference level. When the counter reaches the specified count time, a
pause is detected and the PDFLAG is set and will generate an interrupt if bit PDMSK is
set to logic 1. The PDFLAG operates independently of bit PDMSK and is only active when
the RDS decoder is switched on when bit PUPD is set to logic 1 and when the RDS
decoder is not idle if synchronization is lost.
See
it counts the duration of the pause. If the pause lasts longer than the value set by the PT
bits, bit PDFLAG is set which in turn generates a hardware interrupt (bit PDMSK set to
logic 1). The threshold level at t
Bit PDFLAG is cleared by a read of byte1R on condition that the read action occurs more
than 500 s after receiving the pause interrupt on the INTX line.
The circuit should ignore short transients where the audio level momentarily rises above
the threshold (at t
A pause is detected by comparing the amplitude of the audio signal with the reference
level selected by the PL bits. The resultant signal PSCO produced by this comparison is
sampled at a frequency of 2341 Hz resulting in signal PSCOn. A pause is detected under
the conditions given by
where N is the number of samples taken over time and PT is the pause time selected by
bus bits PT. When a pause is detected, the integrator will be reset. The integrator value
cannot be less than zero; therefore if in
becomes larger than the first SUM, the output of the integrator remains at zero.
Suppose that PT = 20 ms, t
count according to
t
2 t
2. After a search, a preset or an AF update, the threshold for comparison is switched to
pause
SUM 0toN
the hysteresis level. The hysteresis level is set by the combination of bits SSL[1:0] and
bit LHSW; see
ADC level starts to run automatically and compares the level every 500 s with the
hysteresis level. Bit LEVFLAG is set if the RSSI level drops below the threshold level
set by bits SSL[1:0] in combination with bit LHSW (see
interrupt is only generated if the corresponding mask bit is set. Bit LHSW allows either
a small or a large hysteresis to be selected which results in the levels of the left RSSI
hysteresis threshold column for bit LHSW = 0 and the right RSSI hysteresis threshold
column; see
then when the algorithm has finished, the threshold level is set to 0. Hence the
LEVFLAG will never be set.
Figure
pause
–
8 t
–
8 t
7. When the peak audio level of the (L+R) drops below the threshold level at t
audio
–
1
audio
Table
2
PSCOn
).
PT
Equation 5
Table
=
Rev. 02 — 9 August 2005
26. When a search or preset is done with the ADC level set to 3
Equation 4
20 ms 2 16 ms 8 1.5 ms
24. The result is a hysteresis as shown in
=
pause
0
as shown in
–
1
= 16 ms and t
is set by the PL bits shown in
8 SUM 0toN
and
Equation
Equation
–
Equation
audio
–
5.
4, the value of the second SUM
1
= 1.5 ms. The pause detector will
6:
PSCOn
=
20 ms
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
=
Table
1
TEA5764UK
26); the hardware
Table
PT
38.
FM radio + RDS
26. Then the
2341
21 of 64
(4)
(5)
(6)
1