XCV1000E-7FG680C Xilinx Inc, XCV1000E-7FG680C Datasheet - Page 73

• Manufacturer Part Number: XCV1000E-7FG680C
• Description: FPGA Virtex™-E Family 331.776K Gates 27648 Cells 400MHz 0.18um (CMOS) Technology 1.8V 680-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-Er

Specifications of XCV1000E-7FG680C

• Package: 680FBGA
• Family Name: Virtex™-E
• Device Logic Gates: 331776
• Device Logic Units: 27648
• Device System Gates: 1569178
• Maximum Internal Frequency: 400 MHz
• Typical Operating Supply Voltage: 1.8 V
• Maximum Number Of User I/os: 512
• Ram Bits: 393216
• Number Of Logic Elements/cells: 27648
• Number Of Labs/clbs: 6144
• Total Ram Bits: 393216
• Number Of I /o: 512
• Number Of Gates: 1569178
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 680-LBGA Exposed Pad
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used, see
worst-case. Precise values are provided by the timing analyzer.
DS022-3 (v2.9.2) March 14, 2003
Production Product Specification
Notes:
1.
Combinatorial Delays
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
Incremental delay routing through transparent latch to
XQ/YQ outputs
BY input to YB output
Sequential Delays
FF Clock CLK to XQ/YQ outputs
Latch Clock CLK to XQ/YQ outputs
Setup and Hold Times before/after Clock CLK
4-input function: F/G Inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
CE input
SR/BY inputs (synchronous)
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Set/Reset
Minimum Pulse Width, SR/BY inputs
Delay from SR/BY inputs to XQ/YQ outputs
(asynchronous)
Toggle Frequency (MHz) (for export control)
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
R
Description
www.xilinx.com
1-800-255-7778
T
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
F5INCK
T
T
T
T
T
T
T
T
F
IFNCTL
IF5CK
CKF5IN
IF6CK
CECK
T
T
T
DICK
T
T
F5INY
CKLO
CKIF5
CKIF6
CKCE
T
BYYB
RCK /
CKDI
ICK
RPW
IF5X
IF6Y
CKO
CKR
TOG
ILO
CKI
IF5
CH
RQ
CL
/
/
/
/
/
/
0.39 / 0
0.55 / 0
0.27 / 0
0.58 / 0
0.25 / 0
0.28 / 0
0.24 / 0
0.19
0.36
0.35
0.35
0.04
0.27
0.19
0.34
0.40
0.56
0.56
0.94
0.39
Min
Virtex™-E 1.8 V Field Programmable Gate Arrays
-
0.55 / 0
0.46 / 0
0.9 / 0
1.3 / 0
0.6 / 0
1.3 / 0
0.6 / 0
0.40
0.76
0.74
0.74
0.11
0.63
0.38
0.78
0.77
416
1.2
1.2
1.9
0.8
Speed Grade
-8
Figure
2. The values listed below are
0.52 / 0
1.0 / 0
1.4 / 0
0.8 / 0
1.5 / 0
0.7 / 0
0.7 / 0
0.42
0.20
0.46
400
0.8
0.8
0.9
0.7
0.9
0.9
1.3
1.3
2.1
0.9
-7
(1)
1.1 / 0
1.5 / 0
0.8 / 0
1.6 / 0
0.8 / 0
0.7 / 0
0.6 / 0
0.47
0.22
0.51
357
0.9
0.9
1.0
0.8
1.0
1.0
1.4
1.4
2.4
1.0
-6
Module 3 of 4
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
MHz
13