8737-11PGI8 IDT, Integrated Device Technology Inc, 8737-11PGI8 Datasheet

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... LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the IDT8737- 11 ideal for clock distribution applications that demand well-defined perfor- mance and repeatability. ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL PIN CONFIGURATION CLK_EN 2 CLK_SEL 3 CLK 4 xCLK 5 PCLK 6 xPCLK TSSOP TOP VIEW PIN DESCRIPTION (1) Symbol Number V 1 Power EE CLK_EN 2 Input CLK_SEL 3 Input CLK 4 Input xCLK 5 Input PCLK ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL CONTROL INPUT FUNCTION TABLE Inputs MR CLK_EN CLK_SEL NOTES: 1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in the CLK_EN Timing Diagram below. ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL POWER SUPPLY CHARACTERISTICS - COMMERCIAL Symbol Parameter V Positive Supply Voltage DD I Power Supply Current EE DC ELECTRICAL CHARACTERISTICS, LVCMOS / LVTTL - COMMERCIAL Symbol Parameter V CLK_EN, CLK_SEL CLK_EN, CLK_SEL Input Current HIGH ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL AC ELECTRICAL CHARACTERISTICS - COMMERCIAL All parameters measured at 500MHz unless noted otherwise; Cycle-to-cycle jitter = jitter on output; the part does not add jitter Symbol Parameter F Output Frequency MAX t Propagation Delay ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL DC ELECTRICAL CHARACTERISTICS, LVPECL- INDUSTRIAL Symbol Parameter I Input Current HIGH PCLK IH xPCLK I Input Current LOW PCLK IL xPCLK V Peak-to-Peak Input Voltage PP V Common Mode Input Voltage CMR V Output Voltage HIGH ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL PARAMETER MEASUREMENT INFORMATION V DD LVPECL -1.3V ± 0.135V EE xCLK, xPCLK CLK, PCLK xQx Qx xQy Qy COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Z = 50Ω 50Ω Output Load Test Circuit ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL PARAMETER MEASUREMENT INFORMATION - CONTINUED xQx Part 1 Qx xQy Part 2 Qy Clock Inputs and Outputs xCLK, xPLK CLK, PCLK xQA0, xQA1, xQB0, xQB1 QA0, QA1, QB0, QB1 ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE-ENDED LEVELS The diagram below shows how the differential input can be wired to accept single-ended levels. The reference voltage V bias resistors R1, R2, and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V in the center of the input voltage swing ...

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... This section provides information on power dissipation and junction temperature for the IDT8737-11. Equations and example calculations are also provided. POWER DISSIPATION: The total power dissipation for the IDT8737-11 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for the ...

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... IDT8737-11 LOW SKEW, ÷ ÷ ÷ ÷ ÷ 1/÷ ÷ ÷ ÷ ÷ 2 DIFFERENTIAL-TO-3.3V LVPECL CALCULATIONS AND EQUATIONS To calculate worst case power dissipation into the load, use the following equations, which assume a 50Ω load and a termination voltage of V For Logic HIGH: V ...

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... COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES Commercial (0°C to +70°C) Blank Industrial (-40°C to +85° Thin Shrink Small Outline Package PGG TSSOP - Green Low Skew, ÷1/ ÷2 Differential-to-3.3V LVPECL 8737-11 Fanout Buffer for SALES: for Tech Support: 800-345-7015 or 408-284-8200 clockhelp@idt.com fax: 408-284-2775 www.idt.com 12 ...