IDT77V1054L25PF IDT, Integrated Device Technology Inc, IDT77V1054L25PF Datasheet - Page 16

• Manufacturer Part Number: IDT77V1054L25PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V1054L25PF

• Data Rate: 25.6/51.2Mbps
• Number Of Channels: 4
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Package Type: TQFP
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

2. COUNTERS
(e.g. software drivers) in evaluating communications conditions. It is
anticipated that these counters will be polled from time to time (user
selectable) to evaluate performance. A separate set of registers exists
for each channel of the PHY.
cell count (without roll over) if the counter is read once/second. The
Symbol Error counter and HEC Error counter were given sufficient size
to indicate exact counts for low error-rate conditions. If these counters
overflow, a gross condition is occurring, where additional counter
resolution does not provide additional diagnostic benefit.
Reading Counters
Further reads may be accomplished in the same manner by writing to
the Counter Select Registers.
IDT77V1054
Quad Port ATM PHY for 25.6 and 51.2 Mbps with 8-bit Utopia 2
• Symbol Error Counters
• Transmit Cell Counters
• Receive Cell Counters
• Receive HEC Error Counters
1. Decide which counter value is desired. Write to the Counter
Select Register(s) (0x06, 0x16, 0x26 and 0x36) to the bit location
corresponding to the desired counter. This loads the High and Low
Byte Counter Registers with the selected counter’s value, and
resets this counter to zero.
NOTE: Only one counter may be enabled at any time in each of the Counter Select
Registers.
2. Read the Counter Registers (0x04, 0x14, 0x24 or 0x34 (low byte))
and (0x05, 0x15, 0x25 or 0x35 (high byte)) to get the value.
Several condition counters are provided to assist external systems
The TxCell and RxCell counters are sized (16 bits) to provide a full
- 8 bits
- counts all invalid 5-bit symbols received
- 16 bits
- counts all transmitted cells
- 16 bits
- counts all received cells, excluding idle cells and HEC
- 5 bits
- counts all HEC errors received
errored cells
ATM Layer
Device
Interface
Utopia
TC sublayer
Figure 14. Line Loopback
16
sublayer
PMD
77v1054 drw 35
Preliminary
Interface
Line