NLXT300ZPE.F4 Intel, NLXT300ZPE.F4 Datasheet - Page 7

• Manufacturer Part Number: NLXT300ZPE.F4
• Manufacturer: Intel

Specifications of NLXT300ZPE.F4

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Datasheet
1. DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output; S = Supply.
Pin #
10
10
12
13
16
14
15
17
18
11
1
2
3
4
5
6
7
8
9
Table 1. Pin Descriptions
XTALOUT
XTALIN
MRING
MODE
TRING
RNEG
MCLK
TPOS
TNEG
RPOS
TGND
TCLK
RCLK
MTIP
GND
DPM
TTIP
Sym
LOS
TV+
N/C
RT
I/O
DO
DO
DO
AO
DO
DO
AO
AO
DI
DI
DI
DI
DI
AI
AI
AI
AI
S
–
S
S
1
Master Clock. A 1.544 or 2.048 MHz clock input used to generate internal clocks. Upon
Loss of Signal (LOS), RCLK is derived from MCLK.
LXT300Z Only: If MCLK is not applied, this pin must be grounded.
Transmit Clock. Transmit clock input. TPOS and TNEG are sampled on the falling edge of
TCLK. If TCLK is grounded, the output drivers enter a high-Z state, except during Remote
Loopback.
Transmit Positive Data. Input for positive pulse to be transmitted on the twisted-pair line or
coax.
Transmit Negative Data. Input for negative pulse to be transmitted on the twisted-pair line.
Mode Select (LXT300Z). Setting MODE High puts the LXT300Z in the Host mode. In the Host
mode, the serial interface is used to control the LXT300Z and determine its status. Setting
MODE Low puts the LXT300Z in the Hardware (H/W) mode. In the Hardware mode, the serial
interface is disabled and hard-wired pins are used to control configuration and report status.
Ground (LXT301Z). Tie to Ground.
Receive Negative Data; Receive Positive Data. Received data outputs. A signal on RNEG
corresponds to receipt of a negative pulse on RTIP and RRING. A signal on RPOS
corresponds to receipt of a positive pulse on RTIP and RRING. RNEG and RPOS outputs are
Non-Return-to-Zero (NRZ). Both outputs are stable and valid on the rising edge of RCLK.
LXT300Z only: In the Host mode, CLKE determines the clock edge at which these outputs are
stable and valid. In the Hardware mode both outputs are stable and valid on the rising edge of
RCLK.
Recovered Clock. This is the clock recovered from the signal received at RTIP and RRING.
Receive Termination (LXT301Z). Connect to RV+ through a 1 k resistor.
Crystal Input; Crystal Output (LXT300Z). An external crystal operating at four times the bit
rate (6.176 MHz for DSX-1, 8.192 MHz for E1 applications with an
18.7 pF load) is required to enable the jitter attenuation function of the LXT300Z. These pins
may also be used to disable the jitter attenuator by connecting the XTALIN pin to the positive
supply through a resistor, and floating the XTALOUT pin.
No Connection (LXT301Z).
Driver Performance Monitor. DPM goes High when the transmit monitor loop (MTIP and
MRING) does not detect a signal for 63 ±2 clock periods. DPM remains High until a signal is
detected.
Loss of Signal. LOS goes High when 175 consecutive spaces have been detected from
receive. LOS returns Low when a mark is detected from the receiver.
Transmit Tip; Transmit Ring. Differential Driver Outputs. These outputs are designed to
drive a 25
step-up transformer without additional components. To drive
75
Transmit Ground. Ground return for the transmit driver power supply TV+.
Transmit Driver Power Supply. +5 VDC power supply input for the transmit drivers. TV+
must not vary from RV+ by more than ±0.3 V.
Monitor Tip; Monitor Ring. These pins are used to monitor the tip and ring transmit outputs.
The transceiver can be connected to monitor its own output or the output of another LXT300Z
or LXT301Z on the board.
coaxial cable, two 2.2
Advanced T1/E1 Short-Haul Transceivers — LXT300Z/LXT301Z
load. The transmitter will drive 100
resistors are required in series with the transformer.
Description
shielded twisted-pair cable through a 1:2
7