TXC-03401BITQ Transwitch Corporation, TXC-03401BITQ Datasheet - Page 34

• Manufacturer Part Number: TXC-03401BITQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-03401BITQ

• Number Of Transceivers: 1
• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

MEMORY MAP DESCRIPTIONS
Address
00
Bit
7
6
5
4
3
2
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Symbol
RXOOF
RXLOC
RXLOS
TXLOC
RXAIS
RXIDL
Receive DS3 Loss of Signal: A receive LOS alarm occurs when the
incoming DS3 data (D3RD) is stuck low for at least 2048 clock cycles
(D3RC). Recovery occurs when two or more ones are detected in the
incoming data bit stream.
Receive DS3 Out of Frame: A receive OOF occurs when, in a sliding win-
dow of 16 F-bits, three F-bits are in error, or when there are M-bit errors in
two frames of a window of three (MOOFW=1) or four (MOOFW=0) consec-
utive frames. Recovery occurs when 16 consecutive error-free F-bits are
detected in the repeating 1001 F-bit framing pattern, followed by the M-bit
pattern of 010 being detected for two consecutive frames. Recovery takes
approximately 0.95 milliseconds, worst case. An OOF also inhibits the per-
formance counters at Addresses 02H, 03H, 04H, 0AH and 0BH. The termi-
nal output during an RXOOF condition is the received data.
Receive DS3 Alarm Indication Signal (AIS): A Receive DS3 AIS condi-
tion is declared, and the RXAIS bit is set to 1, when RXOOF is 0 and all of
the following events have occurred during a frame: the three C-bits in each
subframe have been 0 for five consecutive frames, at least 95% of the pay-
load of each subframe has contained a repeating 1010.... bit sequence
which begins after each overhead bit for five consecutive frames, and the
latest X-bit received is the sixteenth or higher to have arrived with a 1 value
in the most recent nineteen X-bits received (i.e., sixteen or more 1 values
have occurred since there was an accumulated total of four 0 values).
Recovery to 0 occurs during the first subsequent subframe when one of
these events could occur but does not. AIS detection conforms to the bit
error rate requirement stated in Bellcore document TR-TSY-000191 (Issue
1, May 1986), "Alarm Indication Signal Requirements and Objectives."
Receive DS3 Idle: A Receive DS3 Idle condition is declared, and the
RXIDL bit is set to 1, when RXOOF is 0 and all of the following events have
occurred during a frame: the C7, C8 and C9 bits in subframe 3 are 0, at
least 95 per cent of the payload of each subframe contains a repeating
1100.... bit sequence which begins after each overhead bit for a period of
one frame, and the latest X-bit received is the sixteenth or higher to have
arrived with a 1 value in the most recent nineteen X-bits received (i.e., six-
teen or more 1 values have occurred since there was an accumulated total
of four 0 values). Recovery to 0 occurs at the end of the first subsequent
frame during which not all of these events occur.
Receive DS3 Loss of Clock: An alarm occurs when there are no transi-
tions in the receive clock (D3RC) for seven or more XCK clock cycles. XCK
clock must be present to count D3RC cycles. Recovery occurs on the first
transition of D3RC.
Transmit DS3 Loss of Clock: An alarm occurs when there are no transi-
tions in the transmit clock (XCK) for seven or more D3RC receive clock
cycles. D3RC clock must be present to count XCK cycles. A failure causes
the receive clock to become the transmit clock. This permits the micropro-
cessor interface and transmitter to continue to function. Recovery occurs
on the first transition of XCK.
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DATA SHEET
Description
TXC-03401B
TXC-03401B-MB
Ed. 6, June 2001
DS3F