SLXT336QE.B3 Intel, SLXT336QE.B3 Datasheet
SLXT336QE.B3
Specifications of SLXT336QE.B3
Related parts for SLXT336QE.B3
SLXT336QE.B3 Summary of contents
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LXT336 Quad T1/E1 Receiver The LXT336 quad receiver is a fully-integrated, quadruple-PCM receiver for both T1 (1.544 Mbps) and E1 (2.048 Mbps) applications. It incorporates four independent receivers in a single 64-pin QFP package. The LXT336 features a differential receiver ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 Pin Assignments & Signal Descriptions\ 2.0 Functional Description 2.1 Receiver Description ...........................................................................................10 2.1.1 Loss Of Signal Detector .........................................................................10 2.1.1.1 E1 LOS Detection......................................................................10 2.1.1.2 T1 LOS Detection......................................................................11 2.1.1.3 Data Recovery Mode LOS Detection ........................................11 2.1.1.4 In-Service Code Violation Monitoring ...
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LXT336 — Quad T1/E1 Receiver Revision History Revision Date 4 Description Datasheet ...
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Figure 1. LXT336 Block Diagram MODE UBS LOS RPOS/ AMI / HDB3 RDATA Unipolar RNEG/ Decoder BPV RCLK MCLK Datasheet Quad T1/E1 Receiver — LXT336 LOS Data Detector Slicers Data Peak Recovery Dectector Clock Recovery RTIP RRING Port 0 Port ...
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LXT336 — Quad T1/E1 Receiver 1.0 Pin Assignments & Signal Descriptions\ Figure 2. LXT336 Pin Assignments and Package Markings MCLK CLKI0 GND UBS0 CLKI1 GND UBS1 GND NC GND VCC NC NC GND VCC NC Package Topside Markings Marking Part ...
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Table 1. LXT336 Pin Descriptions Pin 1 Sym I/O # Master Clock Input. An independent and free-running 2.048 or 1.544 MHz clock input generates the internal reference clocks for all Receivers. On Loss of Signal (LOS), the LXT336 derives RCLKx ...
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LXT336 — Quad T1/E1 Receiver Table 1. LXT336 Pin Descriptions (Continued) Pin 1 Sym I/O # Mode Select Input. In unipolar mode, if this pin is pulled Low, all transceivers operate in E1 mode using AMI decoding. With this pin ...
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Table 1. LXT336 Pin Descriptions (Continued) Pin 1 Sym I GND S Ground. 47 CLKI3 DI Clock Input - Port 3. See CLKI0, pin Not Connected. Must be left open. Receive Negative Data/Bipolar Violation ...
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LXT336 — Quad T1/E1 Receiver 2.0 Functional Description The LXT336 quad receiver is a fully-integrated, PCM receiver for both 1.544 Mbps (DSX-1) and 2.048 Mbps (E1) applications. The MCLK frequency and the MODE pin input level set the mode of ...
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The receiver monitor loads a digital counter at the RCLK frequency. The monitor increments the counter with each received 0 (space), and resets with each received 1 (mark). Any signal 21 dB below the nominal 0 dB ...
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LXT336 — Quad T1/E1 Receiver 3.0 Application Information The LXT336 is well suited for both line interface equipment and monitoring applications. The following paragraphs describe the recommended configuration for these applications. 3.1 Monitoring Applications Figure 3 shows a typical configuration ...
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Figure 3. Typical Monitoring Application 432 432 Cable Impedance E1, 120 T1, 100 3.1.1 Receive Line Interface Applications Figure 4 shows the typical LXT336 configuration for receive line interface applications. A 1:1 transformer is used in combination ...
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LXT336 — Quad T1/E1 Receiver Figure 4. Typical Receive Line Interface Application Values Cable Impedance 120 37.5 60 Resistor values are ...
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Table 2. Transformer Specifications Primary Inductance Turns Ratio mH (min.) 1:2 or 1:1 1.2 1. This parameter is application dependent. Datasheet Quad T1/E1 Receiver — LXT336 Leakage Interwinding Inductance Capacitance H pF (max.) (max.) 0.60 30 Dielectric DCR Breakdown Voltage ...
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LXT336 — Quad T1/E1 Receiver 4.0 Test Specifications Note: The minimum and maximum values in represent the performance specifications of the LXT336 and are guaranteed by test except, where noted, by design or other correlation methods. Table 3. Absolute Maximum ...
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Table 5. DC Characteristics (Over Recommended Range) (Continued) Parameter Low level input voltage High level input voltage MODE input pin Midrange input voltage Low level input current High level input current E1 operation Total power 3 dissipation T1 operation Power ...
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LXT336 — Quad T1/E1 Receiver Table 6. E1 Receive Characteristics (Over Recommended Range) (Continued) Parameter 51 kHz–102 kHz 102–2048 kHz 6 Receiver return loss 2048 kHz–3072 kHz 1. Typical figures are at 25 °C and are for design aid only; ...
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Table 8. Timing Characteristics (Over Recommended Range) Parameter Master clock frequency Master clock tolerance Master clock duty cycle 5 Receive clock capture range 2 Receive clock duty cycle 2 Receive clock pulse width Receive clock pulse width low time Receive ...
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LXT336 — Quad T1/E1 Receiver Figure 6. E1 Jitter Tolerance—G.823 1000 UI 100 1 1 LXT336 Jitter Tolerance (typical) 3 ...
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Figure 7. T1 Jitter Tolerance—GR-499-CORE Category II 1000 100 GR-499-CORE Category 0 Table 9. Relevant Recommendations Recommendation G.703 Physical/electrical characteristics of hierarchical digital interfaces G.704 Functional characteristics of interfaces associated ...
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LXT336 — Quad T1/E1 Receiver 5.0 Mechanical Specifications Figure 8. Package Specifications Quad Flat Pack • Part Number: LXT336QE • 64-pin QFP • Extended Temperature Range -40°C - +85°C for sides with even ...