EELXT332PE.G2 S L8L8 Intel, EELXT332PE.G2 S L8L8 Datasheet - Page 10

• Manufacturer Part Number: EELXT332PE.G2 S L8L8
• Manufacturer: Intel

Specifications of EELXT332PE.G2 S L8L8

• Operating Supply Voltage (typ): 5V
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

LXT332 — Dual T1/E1 Line Interface Unit with Crystal-less Jitter Attenuation
10
1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power
QFP
Pin
39
40
41
42
43
44
1
2
3
4
5
6
Supply.
Table 1.
PLCC
Pin
10
12
11
1
2
3
4
5
6
7
8
9
Host Mode and Bipolar Host Mode Pin Descriptions
(Bipolar)
(Bipolar)
(Bipolar)
(Bipolar)
Symbol
RNEG0
TNEG0
RPOS0
TRSTE
TPOS0
RCLK0
TCLK0
MCLK
SCLK
VCQ0
INT1
INT0
DI/O
I/O
DO
DO
DO
DO
DO
DI
DI
DI
DI
DI
DI
1
Tristate Output Enable. When held High, forces all output pins to high-Z (tri-state).
When held Low, Bipolar I/O mode is selected. In this mode, the framer interface is
bipolar (TPOS/TNEG and RPOS/RNEG), and the B8ZS/HDB3 encoders are disabled.
When clocked by MCLK, Unipolar I/O mode is selected. In this mode, the framer
interface is unipolar (TDATA and RDATA), and the TNEG and RNEG pins are re-
mapped. The TNEG pins are re-mapped as Encoder Enables (ECE) to individually
enable the B8ZS/HDB3 encoder/decoder for each port. The RNEG pins are re-
mapped as Bipolar Violation (BPV) indicators to report BPVs detected at the respective
ports.
Transmit Clock - Port 0. 1.544 MHz for T1, 2.048 MHz for E1. The port 0 transmit
data inputs are sampled on the falling edge of TCLK0.
Transmit Positive and Negative Data - Port 0. In the Bipolar I/O mode, these pins
are the positive and negative sides of a bipolar input pair for
port 0. Data to be transmitted onto the twisted-pair line is input at these pins.
Receive Positive and Negative Data - Port 0. In the Bipolar I/O mode, these pins are
the data outputs from port 0. A signal on RNEG corresponds to receipt of a negative
pulse on RTIP/RRING. A signal on RPOS corresponds to receipt of a positive pulse on
RTIP/RRING. RNEG/RPOS outputs are Non Return-to-Zero (NRZ). The CLKE pin
determines the clock edge at which these outputs are stable and valid.
Receive Clock - Port 0. Normally, this clock is recovered from the input signal. Under
Loss of Signal (LOS) conditions, RCLK0 is derived from MCLK.
Serial Clock. SCLK shifts data into or out of the serial interface register of the selected
port.
Violation Insert, High Frequency Clock, or QRSS - Port 0. The function of this pin is
selected by the VCQE pin.
When VCQE is High, the Bipolar Violation (BPV) insertion function is selected. VCQ0
is an input that is sampled on the falling edge of TCLK0 to control BPV insertion. When
VCQ0 is High, a BPV is inserted at the next available mark transmitted from port 0. A
Low-to-High transition is required for each subsequent BPV insertion. B8ZS and HDB3
zero suppression codes are not violated.
When VCQE is Low, the High Frequency Clock (HFC) function is selected. VCQ0
outputs a HFC (12.352 MHz for T1, 16.384 MHz for E1) tied to the jitter attenuated
clock of the port 0. If no JA clock is available, the HFC is locked to the 8x receive
timing recovery clock.
When VCQE is clocked with MCLK, the Quasi Random Signal Source (QRSS) function
is selected. A High on VCQ0 enables the QRSS detection circuit and causes the
LXT332 to transmit the QRSS pattern onto the twisted-pair line from port 0. For error-
free QRSS transmission, TPOS0 must be held Low. To insert errors into the pattern,
TPOS0 must transition from Low to High (TPOS0 is sampled on the falling edge of
MCLK). A Low to High transition is required for each subsequent violation insertion.
B8ZS and HDB3 zero suppression codes are not violated.
Interrupt Outputs. The interrupt outputs go Low to flag the host processor that the
respective port has changed state. INT0 and INT1 are open drain outputs. Each
interrupt signal must be tied to VCC through a resistor.
Master Clock. The master clock (1.544 MHz for T1, 2.048 MHz for E1) must be
independent, free-running, continuously active and jitter free for receiver operation.
Note that MCLK cannot be derived from RCLK because during a Loss of Signal (LOS)
condition, transceiver timing is based on MCLK.
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