82V2048DAG IDT, Integrated Device Technology Inc, 82V2048DAG Datasheet - Page 15

• Manufacturer Part Number: 82V2048DAG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DAG

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

Table-5 Configuration of the Line Code Rule
Table-6 LOS Condition in Clock Recovery Mode
1.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
2.4.3
when the device is configured in single rail mode. B8ZS rules for T1 and
HDB3 rules for E1 are enabled by setting bit CODE in register GCF to ‘0’
or pulling pin CODE low. AMI rule is enabled by setting bit CODE in
register GCF to ‘1’ or pulling pin CODE high. The settings affect all eight
channels.
available by setting bit SINGn in register e-SING to ‘1’ (to activate bit
CODEn in register e-CODE) and programming bit CODEn to select line
code rules in the corresponding channel: ‘0’ for B8ZS/HDB3, while ‘1’ for
AMI. In this case, the value in bit CODE in register GCF or pin CODE for
global control is unaffected in the corresponding channel and only affect
in other channels.
register GCF, bit CODEn in register e-CODE and pin CODE are ignored.
2.4.5
recovery, as shown in Table-7.
2.4.6
HDB3 code violation, as shown in Figure-7,
the three kinds of errors are reported in both host mode and hardware
mode with B8ZS/HDB3 line code rule used. In host mode, the e-CZER
Detected
LOS levels at device (RTIPn, RRINGn) with all ones signal. For more detail regarding the LOS parameters, please refer to
Cleared
Selectable B8ZS/HDB3 and AMI line coding/decoding is provided
Individual line code rule selection for each channel, if needed, is
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
Alarm Indication Signal is available only in host mode with clock
The device can detect excessive zeros, bipolar violation and B8ZS/
CODE
LOS
LOS
High
Low
B8ZS/HDB3/AMI LINE CODE RULE
ALARM INDICATION SIGNAL (AIS) DETECTION
ERROR DETECTION
Continuous Intervals
All channels in B8ZS/HDB3
All channels in AMI
Amplitude
Amplitude
Hardware Mode
Density
Line Code Rule
(1)
(1)
below typical 200 mVp
12.5% (16 marks in a sliding 128-bit
period) with no more than 99 contin-
uous zeros
exceed typical 250 mVp
ANSI T1.231 for T1
Figure-8
175
and Figure-9. All
CODE in GCF
0
0
1
1
0
1
below typical 200 mVp
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
exceed typical 250 mVp
15
2.4.4
the received signal on receiver line before the transformer (measured on
port A, B shown in Figure-12). The loss condition is reported by pulling
pin LOSn high. At the same time, LOS alarm registers track LOS condi-
tion. When LOS is detected or cleared, an interrupt will generate if not
masked. In host mode, the detection supports the ANSI T1.231 for T1
mode, ITU G.775 and ETSI 300 233 for E1 mode. In hardware mode, it
supports the ITU G.775 and ANSI T1.231.
when bit AISE in register GCF is set to ‘0’ or output all ones as AIS
(alarm indication signal) when bit AISE is set to ‘1’. The RCLKn is
replaced by MCLK only if the bit AISE is set.
and e-CODV are used to determine whether excessive zeros and code
violation are reported respectively. When the device is configured in AMI
decoding mode, only bipolar violation can be reported.
pin CVn/RDNn is used as error report output (CVn pin).
rized in Table-8.
CODEn in e-CODE
The configuration of the line code rule is summarized in Table-5.
The Loss of Signal Detector monitors the amplitude and density of
Table-6
During LOS, the RDPn/RDNn continue to output the sliced data
The error detection is available only in single rail mode in which the
The configuration and report status of error detection are summa-
G.775 for E1
Standard
32
LOSS OF SIGNAL (LOS) DETECTION
0/1
0/1
0
1
1
0
summarizes the conditions of LOS in clock recovery mode.
Host Mode
Receiver Characteristics on page
SINGn in e-SING
INDUSTRIAL TEMPERATURE RANGES
below typical 200 mVp
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
exceed typical 250 mVp
0
1
0
1
1
1
ETSI 300 233 for E1
2048 (1 ms)
All channels in B8ZS/HDB3
All channels in AMI
CHn in AMI
CHn in B8ZS/HDB3
48.
Line Code Rule
Signal on
LOSn
High
Low