82V2048DAG IDT, Integrated Device Technology Inc, 82V2048DAG Datasheet - Page 50

• Manufacturer Part Number: 82V2048DAG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2048DAG

• Screening Level: Industrial
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

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2.
3.
4.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
TRANSCEIVER TIMING CHARACTERISTICS
Transmit Path
Receive Path
Clock recovery is disabled in this mode.
RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 UI dis-
Relative to nominal frequency, MCLK =
placement for E1 per ITU G.823).
For all digital outputs. C load = 15 pF
Symbol
t1
t2
t4
t5
t6
t7
t8
t9
MCLK Frequency
MCLK Tolerance
MCLK Duty Cycle
TCLK Frequency
TCLK Tolerance
TCLK Duty Cycle
Transmit Data Setup Time
Transmit Data Hold Time
Delay time of OE low to driver High-Z
Delay time of TCLK low to driver High-Z
Clock Recovery Capture Range
RCLK Duty Cycle
RCLK Pulse Width
RCLK Pulse Width Low Time
RCLK Pulse Width High Time
Rise/Fall Time
Receive Data Setup Time
Receive Data Hold Time
RDPn/RDNn Pulse Width (MCLK = High)
E1:
T1:
E1:
T1:
E1:
T1:
E1:
T1:
E1:
T1:
E1:
T1:
E1:
T1:
E1:
T1:
E1:
T1:
±
100 ppm
(3)
(2)
(2)
Parameter
(1)
(4)
50
-100
Min
457
607
203
259
203
259
200
200
200
200
200
300
-50
40
10
40
40
40
40
5
INDUSTRIAL TEMPERATURE RANGES
2.048
1.544
2.048
1.544
± 180
± 80
Typ
488
648
244
324
244
324
244
324
244
324
244
324
44
50
Max
100
+50
519
689
285
389
285
389
60
90
48
60
30
1
MHz
MHz
MHz
MHz
Unit
ppm
ppm
ppm
ppm
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%