RC82545GM Intel, RC82545GM Datasheet
RC82545GM
Specifications of RC82545GM
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RC82545GM Summary of contents
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... Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the de- vice. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. Datasheet — PHY ability to automatically detect ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Document Scope................................................................................................... 2 1.2 Reference Documents...........................................................................................2 1.3 Product Code ........................................................................................................3 2.0 Additional 82545GM Features............................................................................................ 5 2.1 PCI ........................................................................................................................ 5 2.2 MAC Specific......................................................................................................... 5 2.3 PHY Specific ......................................................................................................... 5 2.4 Host Offloading...................................................................................................... 5 2.5 Manageability ........................................................................................................6 ...
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Networking Silicon 4.2.2 Tristate Mode Using JTAG (TAP)........................................................... 21 5.0 Voltage, Temperature, and Timing Specifications ........................................................... 23 5.1 Targeted Absolute Maximum Ratings ................................................................. 23 5.2 Recommended Operating Conditions ................................................................. 23 5.3 DC Specifications................................................................................................ 24 5.4 AC Characteristics .............................................................................................. ...
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... The Intel 82545GM integrates Intel’s fourth generation gigabit MAC and PHY to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps Mbps. In addition, it provides a 64-bit wide direct Peripheral Component Interconnect (PCI) 2 ...
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... Networking Silicon The 82545GM is packaged 364-ball grid array and footprint compatible with ® the Intel 82544GC Gigabit Ethernet Controller. Figure 1. Gigabit Ethernet Controller Block Diagram Design For Test Interface External TBI Interface LED's S/W Defined Pins 1.1 Document Scope ...
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... IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers (IEEE). ® • Intel Ethernet Controllers Timing Device Selection Guide, AP-419. Intel Corporation. 1.3 Product Code The product ordering code for the 82545GM is: RC82545GM. The product ordering code for the lead-free 82545GM is: PC82545GM. Datasheet Networking Silicon — 82545GM 3 ...
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Additional 82545GM Features 2.1 PCI Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands as well as PCI-X MRD, MRB, and MWB commands 2.2 MAC Specific Low-latency transmit and receive queues Mechanism available for reducing interrupts generated ...
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Networking Silicon 2.5 Manageability On-board SMB port Preboot eXecution Environment (PXE) Flash interface support (32-bit nd 64-bit) SNMP and RMON statistic counters SDG 3.0, WfM 2.0, and PC2001 compliance Wake on LAN support 2.6 Additional Device Internal PLL ...
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... LOM designs easier • Single port or dual port implementation on the same board with minor option changes • Offers lowest geometry to minimize power and size while maintaining Intel quality reliability standards • Simple thermal design • Lower power requirements • ...
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... Signal Descriptions Note: The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 3.1 Signal Type Definitions The signals of the 82545GM controller are electrically defined as follows: ...
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Networking Silicon 3.2.1 PCI Address, Data and Control Signals Symbol Type AD[63:0] TS CBE[7:0]# TS PAR TS PAR64 TS FRAME# STS IRDY# STS TRDY# STS 10 Name and Function Address and data signals are multiplexed on the same ...
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Symbol Type STOP# STS IDSEL# I DEVSEL# STS VIO P 3.2.2 Arbitration Signals Symbol Type REQ64# TS ACK64# TS REQ# TS GNT# I LOCK# I 3.2.3 Interrupt Signal Symbol Type INTA# TS Datasheet Name and Function Stop. The Stop signal ...
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Networking Silicon 3.2.4 System Signals Symbol Type CLK I M66EN I RST# I LAN_ PWR_ I GOOD 3.2.5 Error Reporting Signals Symbol Type SERR# OD PERR# STS 3.2.6 Power Management Signals Symbol Type PME# OD AUX_PWR I 12 ...
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Impedance Compensation Signals Symbol Type ZN_COMP I/O ZP_COMP I/O 3.2.8 SMB Signals Note: A pull-up resistor with a recommended value of 4.7 KΩ should be placed along the SMB. A precise value may be calculated from the SMB specification. ...
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Networking Silicon 3.4 Flash Interface Signals Symbol Type FL_ADDR O [18:0] FL_CS# O FL_OE# O FL_WE# O FL_DATA TS [7:1] FL_DATA[0 ]/LAN_ TS DISABLE# 3.5 Miscellaneous Signals 3.5.1 LED Signals Symbol Type ACT# O LINK# O LINK100# O ...
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PHY Signals 3.6.1 Crystal Signals Symbol Type XTAL1 I XTAL2 O 3.6.2 Analog Signals Symbol Type REF P MDI[0]+/- A MDI[1]+/- A MDI[2]+/- A MDI[3]+/- A Datasheet Name and Function Crystal One. The Crystal One pin ...
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Networking Silicon 3.7 Serializer / Deserializer (SERDES) Signals Symbol Type RX +/- I TX +/- O SIG_ I DETECT 3.8 JTAG Test Interface Signals Symbol Type JTAG_TCK I JTAG_TDI I JTAG_TDO O JTAG_TMS I JTAG_ I TRST# CLK_VIEW ...
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Digital Supplies Symbol Type VDDO P DVDD P 3.9.3 Analog Supplies Symbol Type AVDDH P AVDDL P 3.9.4 Ground and No Connects Symbol Type GND Reserved R Datasheet Name and Function 3.3 V I/O Power Supply. ...
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Test Port Functionality 4.1 XOR Testing A common board or system-level manufacturing test for proper electrical continuity between a silicon component and the board is some type of cascaded-XOR or NAND tree test. The 82545GM implements an XOR tree ...
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Networking Silicon I/O pins with dual-mode function for XOR test: Pin Name FLSH_CE_N When XOR tree test is selected, the following pin behavior(s) occur: • Output drivers for the pins listed as tested are all placed in high-impedance ...
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Pins not included in XOR test tree: • JTAG (TAP) interface: TRST_N, TCK, TDO, TMS, and TDO • Test mode decode controls TEST_DM_N, EWRAP, CLK_BYP_N, CLK_VIEW, and SDP_B[7] • Each internal PHY's analog signals including PHYREF, MDI +/-, and PHY_HSDACP/N ...
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... Voltage, Temperature, and Timing Specifications Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. 5.1 Targeted Absolute Maximum Ratings Table 2. Absolute Maximum Ratings ...
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Networking Silicon Table 3. Recommended Operating Conditions Symbol Input rise/fall time (normal input) tr/tf input rise/fall time (Schmitt input) Operating temperature range TA (ambient) TJ Junction temperature a. Sustained operation of the device at conditions ...
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Table 5.b Unplugged/No Link a Typ Icc (mA Total Device 250 mW Power a. Typical conditions: operating temperature (TA nominal voltages, moderate network traffic at full duplex, and ...
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Networking Silicon Table 5.d D3cold / Wake a Typ Icc (mA Subsystem 3.3 V Current a. Typical conditions: operating temperature (TA nominal voltages, moderate network traffic ...
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Table 6.b Complete Subsystem (Reference SERDES Design) Including LED, Regulator Circuits (no optics) D3cold Wake Disabled (Auxiliary Power) Typ Icc (mA Subsystem 3.3 V Current NOTE: In fiber/optical application or SERDES ...
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Networking Silicon Table 7. I/O Characteristics Symbol Output capacitance OUT C Pull-up/down Resistor value PUD a. TTL3 signals include: EE_DI, EE_SK, EE_CS, and JTAG_TDO. TTL6 signals include: FL_CE#, CLK_VIEW, FL_DATA[7:0], FL_ADDR[18:0], FL_OE#, and FL_WE#. TTL12 ...
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Table 10. Link Interface Clock Requirements Symbol a fGTX GTX_CLK frequency a. GTX_CLK is used externally for test purposes only. Table 11. EEPROM Interface Clock Requirements Symbol fSK Table 12. AC Test Loads for General Output Pins Symbol CL TDO ...
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... Differential Input R IN Impedance 5.6 Timing Specifications Note: Timing specifications are preliminary and subject to change. Verify with your local Intel sales office that you have the latest information before finalizing a design. 5.6.1 PCI/PCI-X Bus Interface 5.6.1.1 PCI/PCI-X Bus Interface Clock Table 15. PCI/PCI-X Bus Interface Clock Parameters ...
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Figure 4. PCI/PCI-X Clock Timing 3.3 V Clock 0.5 Vcc 0.4 Vcc 0.3 Vcc 5.6.1.2 PCI/PCI-X Bus Interface Timing Table 16. PCI/PCI-X Bus Interface Timing Parameters Symbol Parameter CLK to signal valid delay: TVAL bussed signals TVAL CLK to signal ...
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Networking Silicon Figure 5. PCI Bus Interface Output Timing Measurement PCI_CLK Output Delay Tri-State Output Figure 6. PCI Bus Interface Input Timing Measurement Conditions PCI_CLK Input Table 13. PCI Bus Interface Timing Measurement Conditions Symbol VTH Input measurement ...
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Figure 7. TVAL (max) Rising Edge Test Load Figure 8. TVAL (max) Falling Edge Test Load 5.6.2 Link Interface Timing 5.6.2.1 Link Interface Rise and Fall Time Table 17. Rise and Fall Times Symbol Parameter TR Clock rise time TF ...
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Networking Silicon Figure 9. Link Interface Rise/Fall Timing 5.6.2.2 Link Interface Transmit Timing Figure 10. Transmit Interface Timing TX_CLOCK TX_DATA[9:0] Table 18. Transmit Interface Timing Symbol GTX_CLK period TPERIOD TBI mode (1000 Mbps) TSETUP Data setup to rising ...
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Link Interface Receive Timing Figure 11. Receive Interface Timing RBC1 RX_DATA[9:0] COM_DET RBC0 Table 19. Transmit Interface Timing Symbol RBC0/RBC1 frequency TREQ TBI mode (1000 Mbps) TSETUP Data setup before rising RBC0/RBC1 THOLD Data hold after rising RBC0/RBC1 TDUTY ...
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Networking Silicon 5.6.3 Flash Interface Figure 12. Flash Read Timing Flash Address [18:0] Table 20. Flash Read Operation Timing Symbol TCE Flash CE# or OE# to read data delay TACC Flash address setup time THOLD Data hold time ...
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Table 21. Flash Write Operation Timing Symbol TWE Flash write pulse width (WE#) TAH Flash address hold time TDS Flash data setup time 5.6.4 EEPROM Interface Table 22. Link Interface Clock Requirements Symbol TPW EE_SK pulse width Table 23. Link ...
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... Figure 14. 82545GM Device Identification Markings RC82545GM YYWW Fnnnnnnnn (c)’ZZ Country NOTE: The dot in the lower left corner indicates the location of pin 1. Datasheet Networking Silicon — 82545GM ® RC82545GM S Unnn Intel©'ZZ YYWW Fnnnnnnnn Country Product Name Date Code Lot Trace Code Copyright Information ...
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Networking Silicon 6.2 Lead-Free Device Identification Figure 15. Lead-Free 82545GM Device Identification Markings Pin 1 Indicator PC82545GM YYWW Xnnnnnnnn (c)’03 (e1) Taiwan 40 int 82545 GM YYWW Xnnnnnnnn Q 542 SAMPLE C ‘ 03 ...
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Package Information The 82545GM device is a 364-lead ball grid array (BGA) measuring 21 mm dimensions are detailed in the figures below. The nominal ball pitch is 1 mm. Figure 16. 82545GM 364-Lead BGA Ball Pad Dimensions Datasheet Detail ...
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Networking Silicon Figure 17. 82545GM Mechanical Specifications 42 1.00 19.00 21.00±0.10 0.20 MAX 1.70 0.30~0.50 (0.36) C 0.25 Datasheet ...
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Thermal Specifications The 82545GM device is specified for operation when the ambient temperature (TA) is within the range of 0° C (minimum ambient temperature) to 70° C (maximum ambient temperature). The maximum junction temperature for the device is 120° ...
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Networking Silicon 6.5 Ball Mapping Diagram Note: The 82545GM device uses five categories of VDD connections: VDDO (3.3 V), AVDDH (Analog 3.3 V), AVDDL (Analog 2.5 V), and DVDD (1.5 V ...
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Table 25. PCI Address, Data, and Control Signals Signal PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] Table 26. PCI Arbitration Signals Signal ...
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Networking Silicon Table 28. System Signals Signal CLK Table 29. Error Reporting Signals Signal SERR# Table 30. Power Management Signals Signal LAN_PWR_ GOOD Table 31. Impedance Compensation Signals Signal ZN_COMP Table 32. SMB Signals Signal SMBCLK Table 33. ...
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Table 34. Flash Interface Signals Signal FL_ADDR[7] FL_ADDR[8] FL_ADDR[9] Table 35. LED Signals Signal ACT# LINK# Table 36. Software Definable Signals Signal SDP[0] SDP[1] Table 37. PHY Signals Signal XTAL1 XTAL2 REF MDI0- Table 38. Serializer/Deserializer (SERDES) Signals Signal RX+ ...
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Networking Silicon Table 40. Power Support Signals Signal CTRL_15 Table 41. Digital Power Signals Signal VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO ...
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Table 43. Grounds and No Connect Signals Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Table ...
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Networking Silicon Table 44. Reserved Signals Signal Reserved[3] Reserved[4] Reserved[5] Reserved[6] Reserved[7] Reserved[8] Reserved[9] Reserved[10] 50 Pin Signal Pin E4 Reserved[14 Reserved[15 Reserved[16 Reserved[17 Reserved[18 Reserved[19] D10 C7 ...