SI3011-F-FSR Silicon Laboratories Inc, SI3011-F-FSR Datasheet - Page 25

• Manufacturer Part Number: SI3011-F-FSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3011-F-FSR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

5.14.1. Ground Start Idle
Ensure the relay in series with TIP is closed by clearing
the TGOE bit (Register 32, bit 1). This enables the DAA
to sense if the CO grounds TIP. Set RG to 1
(Register 32, bit 0) so that no current flows through the
relay connecting RING to ground.
5.14.2. DAA Requests Line Seizure
With TGOE set to zero, seize the line by closing the
relay in series with RING (clear the RG bit,
Register 32, bit 0). The CO detects this current flowing
R102, R103,
Table 14. Component Values for the Ground
Figure 20. Typical Application Circuit for
Symbol
R101
R106
R104
R105
RL1
Ground Start Support on the SI3050
U3
TGDEb
VD
RGb
Start Support Schematic
R102
-24V
1.5 k, 1/10 W, ±5% Venkel, SMEC,
1 k, 1/10 W, ±5%
10 k, 1/2 W, ±5%
200 , 2 W, ±5%
R105
R103
1
2
3
4
PS2501L-1
AQW210S
RL1
1
2
3
4
Opto-Relay
Value
TGDb
R104
8
7
6
5
8
7
6
5
1
2
U3
1
2
VD
Opto-Isolator
R101
R106
4
3
Venkel, SMEC,
Venkel, SMEC,
Venkel, SMEC,
NEC, Fairchild
4
3
Aromat, NEC
Supplier(s)
Panasonic
Panasonic
Panasonic
Panasonic
TIP
RING
Rev. 1.11
on RING and grounds TIP. This sets the TGD bit
(Register 32, bit 2). The DAA may then be taken
off-hook and the relay in series with RING opened (clear
the RG bit). The call continues as in loop-start mode.
5.14.3. CO Requests Line Seizure
In a normal on-hook state, the relay in series with TIP
should be closed, connecting the –24 V isolated supply.
The CO grounds TIP to request line seizure, causing
current to flow. The opto-isolator U3 (see Figure 20 on
page 25) detects this current and sets the TGD bit
(Register 32, bit 2). This bit remains high as long as
current is detected. The TGDI bit (Register 4, bit 1) is a
sticky bit, and remains high until cleared. A hardware
interrupt on the AOUT/INT can be made to occur when
TIP current begins to flow by enabling the TGDM bit
(Register 3, bit 1). Clear the interrupt by writing 0 to the
TGDI bit (Register 4 bit 1). The DAA may then be taken
off-hook and the call continued as in loop-start mode.
5.15. Interrupts
The AOUT/INT pin can be used as a hardware interrupt
pin by setting the INTE bit (Register 2, bit 7). When this
bit is set, the analog output used for call progress
monitoring is not available. The default state of this
interrupt output pin is active low, but active high
operation can be enabled by setting the INTP bit
(Register 2, bit 6). This pin is an open-drain output
when the INTE bit is set and requires a 4.7 k pullup or
pulldown for correct operation. If multiple INT pins are
connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k Bits 7–0 in
Register 3 and bit 1 in Register 44 can be set to enable
hardware interrupt sources. When one or more of these
bits is set, the AOUT/INT pin goes into an active state
and stays active until the interrupts are serviced. If more
than one hardware interrupt is enabled in Register 3,
use software polling to determine the cause of the
interrupts. Register 4 and bit 3 of Register 44 contain
sticky interrupt flag bits. Clear these bits after servicing
the interrupt.
Registers 43 and 44 contain the line current/voltage
threshold interrupt. This interrupt is triggered when the
measured line voltage or current in the LVS or LCS2
registers,
(Register 44, bit 2), crosses the threshold programmed
into the CVT[7:0] bits. With the CVP bit, the interrupt
can be programmed to occur when the measured value
rises above or falls below the threshold. Only the
magnitude of the measured value is used for
comparison to the threshold programmed into the
CVT[7:0] bits. Therefore, only positive numbers should
be used as a threshold.
as
Si3050 + Si3011
selected
by
the
CVS
bit
25