LULXT9785MBC.D0-865118 Cortina Systems Inc, LULXT9785MBC.D0-865118 Datasheet - Page 162

• Manufacturer Part Number: LULXT9785MBC.D0-865118
• Manufacturer: Cortina Systems Inc

Specifications of LULXT9785MBC.D0-865118

• Lead Free Status / RoHS Status: Compliant

LXT9785/LXT9785E
Datasheet
249241, Revision 11.0
16 April 2007
5.2.2
5.2.2.1
5.2.3
5.2.4
Cortina Systems
The recommended implementation is to break the VCC plane into two sections. The
digital section supplies power to the VCCD and VCCIO pins of the LXT9785/LXT9785E.
The analog section supplies power to the VCCA pins. The break between the two planes
should run underneath the device. In designs with more than one the LXT9785/
LXT9785E, a single continuous analog VCC plane can be used to supply them all.
The digital and analog VCC planes should be joined at one or more points by ferrite
beads. The beads should produce at least a 100 Ω impedance at 100 MHz. Beads should
be placed so that current flow is evenly distributed. The maximum current rating of the
beads should be at least 150% of the current that is actually expected to flow through
them. A bulk cap (2.2 -10μF) should be placed on each side of each bead.
In addition, a high-frequency bypass cap (0.01 μF) should be placed near each analog
VCC pin.
Power and Ground Plane Layout Considerations
Great care needs to be taken when laying out the power and ground planes.
Chassis Ground
For ESD reasons, it is a good design practice to create a separate chassis ground that
encircles the board and is isolated via moats and keep-out areas from all circuit-ground
planes and active signals. Chassis ground should extend from the RJ-45 connectors to
the magnetics, and can be used to terminate unused signal pairs (Bob Smith termination).
In single-point grounding applications, provide a single connection between chassis and
circuit grounds with a 2 kV isolation capacitor. In multi-point grounding schemes (chassis
and circuit grounds joined at multiple points), provide 2 kV isolation to the Bob Smith
termination.
MII Terminations
Series termination resistors are required on all the SS-SMII output signals driven by the
LXT9785/LXT9785E. Special trace layout consideration should be used when using the
SMII interface. Keep all traces orthogonal and as short as possible. Whenever possible,
route the clock and sync traces evenly between the longest and shortest data routes. This
minimizes round-trip, clock-to-data delays and allows a larger margin to the setup and
hold requirements.
Twisted-Pair Interface
Use the following standard guidelines for a twisted-pair interface:
®
• Follow the guidelines in the Cortina Systems
• Keep the digital VCC plane away from the TPFOP/N and TPFIP/N signals, the
• Place the layers so the TPFOP/N and TFPIP/N signals can be routed close to the
• Place the magnetics as close as possible to the LXT9785/LXT9785E.
• Keep transmit pair traces as short as possible; both traces should have the same
• Avoid vias and layer changes as much as possible.
LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers
8-Port 10/100 Mbps PHY Transceivers Design and Layout Guide for locating the split
between the digital and analog VCC planes.
magnetics, and the RJ-45 connectors.
ground plane. For EMI reasons, it is more important to shield TPFOP/N than TPFIP/N.
length.
®
LXT9785 and LXT9785E Advanced
5.2 General Design Guidelines
Page 162