CY7C9689A-AI Cypress Semiconductor Corp, CY7C9689A-AI Datasheet - Page 25

• Manufacturer Part Number: CY7C9689A-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
CY7C9689A Receiver TTL Switching Characteristics, FIFO Enabled
CY7C9689A Transmitter TTL Switching Characteristics, FIFO Bypassed
CY7C9689A Receiver TTL Switching Characteristics, FIFO Bypassed
Note
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
20. The period of t
RXOE
RXZA
TRA
REFDS
REFDH
REFENS
REFENH
REFCES
REFCEH
REFZA
REFOE
REFAZ
ROS
RXCLKOP
RXCLKOD
RXCLKOR
RXCLKOF
RXENS
RXENH
RXZA
RXOE
RXAZ
Parameter
Parameter
Parameter
[20]
[16]
[16]
ROS
Sample of CE LOW by RXCLK↑ to Output Valid,
or Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs Valid
Sample of CE HIGH by RXCLK↑ to Output in High-Z,
or Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs in High-Z
Flag Access Time From REFCLK↑ to Output
Write Data Set-up Time to REFCLK↑
Write Data Hold Time from REFCLK↑
Transmit Enable Set-up Time to REFCLK↑
Transmit Enable Hold Time from REFCLK↑
Transmit Chip Enable (CE) Set-up Time to REFCLK↑
Transmit Chip Enable (CE) Hold Time from REFCLK↑
Sample of CE LOW by REFCLK↑, Output High-Z to Active HIGH or LOW
Sample of CE LOW by REFCLK↑ to Flag Output Valid
Sample of CE HIGH by REFCLK↑ to Flag Output High-Z
RXCLK Clock Output Frequency—100 to 200 MBaud 8-bit Operation
(SPDSEL is HIGH and BYTE8/10 is HIGH)
RXCLK Clock Output Frequency—50 to 100 MBaud 8-bit Operation
(SPDSEL is LOW and BYTE8/10 is HIGH)
RXCLK Clock Output Frequency—100 to 200 MBaud 10-bit Operation
(SPDSEL is HIGH and BYTE8/10 is LOW)
RXCLK Clock Output Frequency—50 to 100 MBaud 10-bit Operation
(SPDSEL is LOW and BYTE8/10 is LOW)
RXCLK Output Period
RXCLK Output Duty Cycle
RXCLK Output Rise Time
RXCLK Output Fall Time
Receive Enable Set-up Time to RXCLK↑
Receive Enable Hold Time from RXCLK↑
Sample of CE LOW by RXCLK↑, Outputs High-Z to Active
Sample of RXEN Asserted by RXCLK↑ to RXDATA Outputs High-Z to Active
Sample of CE LOW by RXCLK↑ to Flag Output Valid
Sample of RXEN Asserted by RXCLK↑ to RXDATA Output Low-Z
Sample of CE HIGH by RXCLK↑ to Flag Output High-Z
Sample of RXEN Deasserted by RXCLK↑ to RXDATA Output High-Z
will match the period of the transmitter PLL reference (REFCLK) when receiving serial data. When data is interrupted, RXCLK may drift to REFCLK +0.2%.
[18]
[18]
Description
Description
Description
[19]
[19]
Over the Operating Range (continued)
Over the Operating Range
Over the Operating Range
Min.
Min.
Min.
8.33
4.16
0.25
0.25
1.5
1.5
1.5
1.5
1.5
1.5
10
25
40
2
4
2
4
2
4
2
0
5
4
1
0
CY7C9689A
16.67
Max.
Max.
Max.
8.33
240
20
20
15
20
20
20
10
60
20
20
2
2
Page 25 of 51
Unit
Unit
Unit
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
[+] Feedback