CY7C9689A-AI Cypress Semiconductor Corp, CY7C9689A-AI Datasheet - Page 35

• Manufacturer Part Number: CY7C9689A-AI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C9689A-AI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02020 Rev. *D
Table 8. HOTLink TAXI Compatible Command Symbols (continued)
Functional Description
The interconnection of two or more CY7C9689A Transceivers
forms a general-purpose communications subsystem capable
of transporting user data at up to 20 MBytes per second over
several types of serial interface media. The CY7C9689A is
highly configurable with multiple modes of operation.
In the transmit section of the CY7C9689A, data moves from
the input register, through the Transmit FIFO, to the 4B/5B
Encoder. The encoded data is then shifted serially out the
OUTx± differential PECL compatible drivers. The bit-rate clock
is generated internally from a 2.5x, 5x, or 10x PLL clock multi-
plier. A more complete description is found in the section
CY7C9689A
Description.
In the receive section of the CY7C9689A, serial data is
sampled by the receiver on one of the INx± differential line
receiver inputs. The receiver clock and data recovery PLL
locks onto the selected serial bit stream and generates an
internal bit-rate sample clock. The bit stream is deserialized,
decoded, and presented to the Receive FIFO, along with a
character clock. The data in the FIFO can then be read either
slower or faster than the incoming character rate. A more
complete description is found in the section CY7C9689A
HOTLink Receive-Path Operating Mode Description.
Note
45. Signals shown as dotted lines represent the differences in timing and active state of signals when operated in Cascade Timing.
10-bit mode (BYTE8/10 is LOW)
CY7C9689A (Transmitter)
A
D
E
8
9
F
[45]
[45]
C
[45]
1
2
3
4
5
6
7
[45]
B
[45]
[45]
0
1
2
3
Command Input
TXCMD[3:0]
HOTLink
Transmit-Path
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
00
01
10
11
Operating
011000 100011
011101 011101
011101 111001
111111 111111
00100 00100
00100 00000
00000 00100
00000 00000
01101 01101
01101 11001
11001 11001
11111 00100
01101 00111
11001 00111
00100 11111
00111 00111
00111 11001
00000 11111
11111 11111
Mode
LM (10-bit SYNC)
The Transmitter and Receiver parallel interface timing and
functionality can be configured to Cascade directly to external
FIFOs for depth expansion, couple directly to registers, or
couple directly to state machines. These interfaces can accept
or output either:
The bit numbering and content of the parallel transmit interface
is shown in
Encoder bypassed, the TXSC/D and RXSC/D bits are ignored.
The HOTLink Transceiver serial interface provides a seamless
interface to various types of media. A minimal number of
external passive components are required to properly
terminate transmission lines and provide LVPECL loads. For
power supply decoupling, a single capacitor (in the range of
0.02 µF to 0.1 µF) is required per power/ground pair. Additional
information on interfacing these components to various media
can be found in the HOTLink Design Considerations appli-
cation note.
• 8-bit characters
• 10-bit characters
• 10-bit pre-encoded characters (pre-scrambled or
• 12-bit pre-encoded characters (pre-scrambled or
pre-encoded)
pre-encoded).
T’T’
T’S’
QQ
SR
HH
HQ
RR
RS
QH
TS
TR
SS
TT
IH
HI
QI
I’I’
II
Table
1. When operated with the 4B/5B, 5B/6B
C
D
1
2
3
4
5
6
7
8
9
A
B
E
F
0
1
2
3
CY7C9689A (Receiver)
Command Output
RXCMD[3:0]
CY7C9689A
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0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
00
01
10
11
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