AM79C2031JC AMD (ADVANCED MICRO DEVICES), AM79C2031JC Datasheet - Page 10

• Manufacturer Part Number: AM79C2031JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C2031JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

VDC
DC Loop Voltage (Output)
The voltage on this output is referenced to VREF and
is proportional to the negative absolute value of the
DC subscriber loop voltage between A and B. This
voltage is a fraction ( ) of the voltage between HPA
and HPB. This pin connects to the IAB pin on the
ASLAC device through external resistor RAB. A
voltage that is significantly more positive than VREF
on the VDC pin indicates that the ASLIC device is in
thermal shutdown.
VLBIAS
Longitudinal Offset Voltage (Input)
The input to this pin is the offset reference voltage for
the ASLIC device longitudinal control loop.
VREF
Analog Reference (Input)
This voltage is provided by the ASLAC device and is
used by the ASLIC device for internal reference
purposes. All analog input and output signals
interfacing to the ASLAC device are referenced to this
pin. Nominally set to 2.1 V.
VTX
Four-Wire Transmit Signal (Output)
The voltage between this pin and VREF is a scaled
version of the AC component of the voltage sensed
between the SA and SB pins. One end of the two-wire
input impedance programming network connects to
VTX. The voltage at VTX swings positive and negative
about VREF.
ASLAC Device
AGND
Analog (Quiet) Ground
VREF is referenced to this ground.
C2–C1
ASLIC Device Control (Outputs)
These ternary logic output pins are dedicated to
controlling the operating state of the ASLIC device.
The levels of these outputs are logic High, logic Low,
and high impedance.
CS
Chip Select (Input, Active Low)
The chip select input (active Low) enables the device
so commands and data can be written to or read from
it. If chip select is held Low for 16 or more DCLK cycles
(independent of MCLK or PCLK), a hardware reset is
executed at the time chip select returns to logic 1.
10
Am79213/Am79C203/031 Data Sheet
P R E L I M I N A R Y
DCLK
Data Clock (Input)
The data clock input shifts data into or out of the
microprocessor interface of the ASLAC device. The
maximum clock rate is 4.096 MHz.
DGND
Digital Ground
Digital ground return
DI/O
Data Input/Output
Control data is serially written into and read out of the
ASLAC device via the DI/O pin, with the most
significant bit first. The data clock (DCLK) determines
the data rate. DI/O is high impedance except when
data is being transmitted from the ASLAC device under
control of CS.
DRA, DRB
Receive PCM Data (Input)
Receive PCM data is received serially on either the
DRA or DRB port, with port selection under user
program control. Data is received, most significant bit
first, in 8-bit PCM or 16-bit linear 2’s complement
bursts every 125 µs at the PCLK rate. The receive
port is unaffected by the setting of the SMODE bit.
(DRB – 44-pin PLCC only.)
DXA, DXB
Transmit PCM Data (Output)
Transmit PCM data is transmitted serially through either
the DXA or DXB port, with port selection under user
control. The transmission data output is available every
125 µs and is shifted out, most significant bit first, in 8-bit
PCM or 16-bit linear 2’s complement bursts at the
PCLK rate. DXA/B are high impedance between bursts
and while the device is in the Inactive state.
For signaling register operation on the PCM highway,
see the SMODE description. (DXB – 44-pin PLCC
only.)
FS
Frame Sync (Input)
The frame sync signal is an 8 kHz pulse that identifies
the beginning of a frame. The ASLAC device
references individual time slots with respect to this
input, which must be synchronized to PCLK.
IAB
Loop Voltage Sense (Input)
The IAB pin is a current summing node referenced to
VREF. An external resistor (RAB) is connected
between this pin and the VDC pin of the ASLIC device,
In normal operation, current flows out of this pin. When