AM79C2031JC AMD (ADVANCED MICRO DEVICES), AM79C2031JC Datasheet - Page 11

• Manufacturer Part Number: AM79C2031JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C2031JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

the ASLIC device is in thermal shutdown, current will
be forced into this pin.
IBAT
Battery Voltage Sense (Input)
The IBAT pin is a current summing node referenced to
AGND and receives a current that is proportional to
the system battery voltage. A sense resistor/capacitor
network is connected between the QBAT pin of the
ASLIC device and the IBAT pin.
IDC
DC Loop Control Current (Output)
The IDC output supplies a current to the ASLIC device
for proportional control of the DC loop current flowing
through the subscriber loop.
IDIF
Longitudinal Sense (Input)
IDIF is a current input pin fed by the IDIF pin of the
ASLIC device. The current in this pin is used by the
ASLAC device for supervisory and diagnostic
functions. The IDIF pin has an internal input resistance
so an external longitudinal noise filter capacitor can be
connected.
INT
Interrupt (Output, Active Low)
A logic 0 on this pin indicates one or more of the bits
in the signaling register has changed states. An
interrupt will be generated when activity is sensed on
any signal in the Signaling Register not masked by the
Mask Register. Once an unmasked activity is sensed,
the INT output will be driven Low and held at that state
until cleared. See the description of configuration
register 6 for operation.
I/O
Control Ports (Input/output)
These control lines are TTL compatible and each can
be programmed as an input or an output. When
programmed as inputs, they can monitor external, TTL
compatible logic circuits. When programmed as
outputs, they can control an external logic device or
they can be connected to pin C3, C4, or C5 of the
ASLIC device to control test relay drivers RY1OUT,
RY2OUT and RY3OUT (I/O
version only). In the Output mode, these pins are
controlled by the I/O
Channel Control Register, MPI Command 17.
IREF
Current Reference
An external resistor (RREF) connected between this
pin and analog ground generates an accurate on-chip
1
, I/O
2
, I/O
3
, I/O
1
, I/O
4
2
, I/O
3
, I/O
3
, and I/O
4
, 44-pin PLCC
4
P R E L I M I N A R Y
bits in the
ASLIC/ASLAC Products
reference current. This current is used by the ASLAC
device in its DC Feed and loop-supervision circuits.
IRTA, IRTB
Ring Trip Sense (Inputs)
These pins are current summing nodes referenced to
VREF. They provide terminations for external resistors
RSR1 and RSR2, which sense the voltages on both
sides of the ringing feed resistor connected to the ring
bus. To determine the ringing current in the loop, the
ASLAC device senses the difference between the
currents in these pins.
ISUM
Metallic Sense (Input)
ISUM is a current input pin and is fed by the ISUM pin
of the ASLIC device. The absolute value of the current
in this pin is used by the ASLAC device for supervisory
and diagnostic functions.
MCLK
Master Clock (Input)
The master clock is used to operate the digital signal
processor. MCLK can be 2.048 MHz, 4.096 MHz or
8.192 MHz. MCLK may be asynchronous to PCLK.
Upon initialization, the MCLK input is disabled and
relevant circuitry is driven by a connection to PCLK.
The MCLK connection may be reestablished under
user control.
PCLK
PCM Clock (Input)
The PCM clock determines the rate at which PCM data
is serially shifted into or out of the PCM ports. PCLK
is an integer multiple of the frame sync frequency. The
maximum clock frequency is 8.192 MHz and the
minimum clock frequency is 128 kHz for companded
data. The minimum clock frequency for linear or
companded data plus signaling data is 256 kHz. The
PCLK clock may be asynchronous to MCLK if the initial
connection state is disabled under user control.
RST
Reset (Input, Active Low)
A logic 0 on this pin resets the ASLAC device to initial
default conditions. It is equivalent to a hardware reset
command. A signal less than 100 ns should not cause
a reset. To ensure proper reset, the minimum length
of a reset pulse is 50 µs.
TSCA, TSCB
Time Slot Control (Open Drain Outputs)
The time slot control outputs are open drain (requiring
an external pull-up resistor to VCCD) and are normally
inactive (high impedance). TSCA is active (Low) when
PCM data is present on DXA, and TSCB is active (Low)
11