AM79Q02JC AMD (ADVANCED MICRO DEVICES), AM79Q02JC Datasheet - Page 34

• Manufacturer Part Number: AM79Q02JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79Q02JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

slot after the last full time slot in the frame will contain
random information and will have the TSC output
turned on. For example, if the PCLK frequency is
1.544 MHz (R = 1) and the transmit clock slot is greater
than 1, the 1-bit fractional time slot after the last full
time slot in the frame will contain random information,
and the TSC output will remain active during the
fractional time slot. In such cases, problems can be
avoided by not using the last time slot.
The PCM data may be user programmed for output
onto either the DXA or DXB por t or both por ts
simultaneously. Correspondingly, either TSCA or
TSCB or both are Low during transmission.
The DXA/DXB and TSCA/TSCB outputs can be
programmed to change either on the negative or
positive edge of PCLK.
Tr a n s m i t d a t a c a n a l s o b e r e a d t h r o u g h t h e
microprocessor interface using Command 47.
Receive Signal Processing
In the receive path (D/A), the digital signal is expanded
(for A-law or µ-law), filtered, converted to analog, and
passed to the VOUT pin. The signal processor
contains an ALU, RAM, ROM, and Control logic to
implement the filter sections. The Z, R, and GR blocks
are user-programmable filter sections with their
coefficients stored in the coefficient RAM, while AR is an
analog amplifier which can be programmed for a 0 dB or
6.02 dB loss. The Z, R, and GR filters can also be
operated from an alternate set of default coefficients
stored in ROM (Commands 24 and 25).
The low-pass filter band limits the signal. The R filter is
composed of a six-tap FIR section operating at a 16 kHz
sampling rate and a one-tap IIR section operating at
8 kHz. It is part of the frequency response correction
network. The Analog Impedance Scaling Network
(AISN) is a user-programmable gain block providing
feedback from VIN to VOUT to emulate different SLIC
input impedances from a single exter nal SLIC
impedance. The Z filter provides feedback from the
transmit signal path to the receive path and is used to
modify the effective input impedance to the system.
The interpolator increases the sampling rate prior to
D/A conversion.
Receive PCM Interface
The receive PCM interface logic controls the reception
of data bytes from the PCM highway, transfers the data
to the A-law/µ-law expansion logic for compressed
signals, and then passes the data to the receive path of
the signal processor. If the data received from the PCM
highway is programmed for linear code, the A-law/µ-law
expansion logic is bypassed and the data is presented
to the receive path of the signal processor directly. The
linear data requires two consecutive time slots, while
the A-law or -law data requires a single time slot.
34
Am79Q02/021/031 Data Sheet
The frame sync (FS) pulse identifies time slot 0 of the
receive frame, and all channels (time slots) are
r e f e r e n c e d t o i t . T h e l o g i c c o n t a i n s u s e r -
programmable Receive Time Slot and Receive Clock
Slot registers. The Time Slot register is 7 bits wide and
allows up to 128 8-bit channels (using a PCLK of
8.192 MHz) in each frame. This feature allows
a n y c l o c k f r e q u e n c y b e t w e e n 128 kHz and
8.192 MHz (2 to 128 channels) in a system.
The Clock Slot register is 3 bits wide and can be
programmed to offset the time slot assignment by 0 to
7 PCLK periods to eliminate any clock skews in the
system. An exception occurs when division of the
PCLK frequency by 64 kHz produces a nonzero
remainder (R), and when the receive clock slot is
greater than R. In that case, the last full receive time
slot in the frame is not usable. If the PCLK frequency
is 1.544 MHz (R=1/8, or 1 clock slot within a time slot),
the receive clock slot can be only 0 or 1 if the last time
slot is to be used. The PCM data can be programmed
for input from the DRA or DRB port.
Analog Impedance Scaling Network (AISN)
The AISN is in the QSLAC device to scale the value of
the external SLIC impedance. Scaling this external
impedance with the AISN (along with the Z filter) allows
matching of many different line conditions using a
single impedance value. Linecards can meet many
different specifications without any hardware changes.
The AISN is a programmable transfer function connected
from VIN to VOUT for each QSLAC device channel. The
AISN transfer function alters the input impedance of the
SLIC device to a new value (Z
where G
G
is the SLIC input impedance without the QSLAC device.
The gain can be varied from –0.9375 to +0.9375 in 31
steps of 0.0625. The AISN gain is determined by the
following equation:
where AISN
There are two special cases to the formula for h
1) a value of AISN = 00000 will specify a gain of 0 (or
cutoff), and 2) a value of AISN = 10000 is a special
case where the AISN circuitry is disabled and VOUT is
connected internally to VIN with a gain of 0 dB. This
allows a Full Digital Loopback state where an input
digital PCM signal is completely processed through
the receive section, looped back, processed through
the transmit section, and output as digital PCM data.
Z
h
AISN
IN
44
is the SLIC echo gain into a short circuit, and ZSL
=
=
ZSL
440
0.0625
i
is the SLIC echo gain into an open circuit,
= 0 or 1
1 G
–
i
=
4
44
0
AISN
h
AISN
i
IN
2
i
):
–
1 G
16
–
440
h
AISN
AISN
: