AM79Q02JC AMD (ADVANCED MICRO DEVICES), AM79Q02JC Datasheet - Page 44

• Manufacturer Part Number: AM79Q02JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79Q02JC

• Lead Free Status / RoHS Status: Supplier Unconfirmed

20, 21. Write/Read SLIC Input/Output Register
22, 23. Write/Read SLIC Input/Output Direction, Read Status Bits
44
(52/53h)
R/W = 0: Write
R/W = 1: Read
(54/55h)
RSVD
Pins CD1, CD2, and C3 through C5 are set to 1 or 0. The data appears latched on the CD1,
CD2, and C3 through C5 SLIC I/O pins, provided they were set in the Output mode (see
Command 22). The data sent to any of the pins set to the Input mode is latched, but does not
appear at the pins. The CD1B bit is only valid if the E1 Multiplex mode is enabled (EE1 = 1).
* Power Up and Hardware Reset (
RSVD
Channel Status (Read status only, write as 0)
Clock Fail (Read status only, write as 0)
I/O Direction (Read/Write)
Pins CD1, CD2, and C3 through C5 are set to Input or Output modes individually. Pins C3–C5
are not available on the Am79Q031 QSLAC device, and C5 is available only on the Am79Q021
QSLAC device.
* Power Up and Hardware Reset (
Command
I/O Data
Command
Input Data
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
CSTAT = 0
CSTAT = 1
CFAIL* = 0
CFAIL = 1
* The CFAIL bit is independent of the Channel Enable Register.
IOD5 = 0*
IOD5 = 1
IOD4 = 0*
IOD4 = 1
IOD3 = 0*
IOD3 = 1
IOD2 = 0*
IOD2 = 1
IOD1 = 0*
IOD1 = 1
Am79Q02/021/031 Data Sheet
Channel is inactive (Standby mode).
Channel is active.
The internal clock is synchronized to frame synch.
The internal clock is not synchronized to frame synch.
C5 is an input
C5 is an output
C4 is an input
C4 is an output
C3 is an input
C3 is an output
CD2 is an input
CD2 is an output
CD1 is an input
CD1 is an output
RSVD
RSVD
D
0
D
0
7
7
RST
RST
CSTAT
) Value = 00h
) Value = 00h
RSVD
D
D
1
1
6
6
CFAIL
CD1B
D
D
0
0
5
5
IOD5
C5
D
D
1
1
4
4
IOD4
D
D
C4
0
0
3
3
IOD3
C3
D
D
1
0
2
2
MPI Command
MPI Command
IOD2
CD2
D
D
0
1
1
1
IOD1
CD1
R/W
R/W
D
D
0
0