DS92LX2121SQE National Semiconductor, DS92LX2121SQE Datasheet - Page 19

• Manufacturer Part Number: DS92LX2121SQE
• Description: SERDES, 10-50MHZ, 40LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2121SQE

• Data Rate: 1.05Gbps
• No. Of Inputs: 21
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 40
• Base Number: 2121
• Operating Temperature Range: -40°C To +85°C
• Serdes Function: Serializer
• Ic Input Type: LVCMOS
• Ic Output Type: LVCMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

(Hex)
Addr
TABLE 1. DS92LX2121 Control Registers
0
1
2
3
4
5
6
7
8
9
A
Reserved
VDDIO Control
I
VDDIO Mode
PCLK_AUTO
I
2
2
C Device ID
C Bus Rate
Reserved
Reserved
I
Reserved
Reserved
Reserved
Reserved
Slave ID
2
Through
DES ID
C Pass-
Name
Reset
TRFB
Bits
7:1
7:3
7:0
7:6
7:0
7:0
7:1
7:1
7:0
7:0
7:0
0
2
1
0
5
4
3
2
1
0
0
0
Field
DEVICE ID
SER ID
RESERVED
STANDBY
DIGITAL
RESET0
DIGITAL RESET1
RESERVED
RESERVED
VDDIO CONTOL
VDDIO MODE
I
THROUGH
RESERVED
PCLK_AUTO
TRFB
RESERVED
I
DES DEV ID
RESERVED
SLAVE DEV ID
RESERVED
RESERVED
RESERVED
RESERVED
2
2
C PASS-
C BUS RATE
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
19
self clear
self clear
Default
0x20'h
0x80'h
0x40'h
0x60'h
0x01'h
0x58
11'b
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
Description
7-bit address of Serializer; 0x58h
(1011_000X) default
0: Device ID is from CAD
1: Register I
Reserved.
Standby mode control. Retains control register data.
Supported only when M/S = 0
0: Enabled. Low-current Standby mode with wake-up
capability. Suspends all clocks and functions.
1: Disabled. Standby and wake-up disabled
1: Digital Reset, retained register value
1: Digital Reset, retains all register values
Reserved.
Reserved.
Auto V
Allows manual setting of V
0: Disable
1: Enable (auto detect mode)
V
Only used when VDDIOCONTROL = 0
0: 1.8V
1: 3.3V
I
0: Disabled
1: Enabled
Reserved.
Switch over to internal 25 MHz oscillator clock in the
absence of PCLK
0: disable
1: enable
Pixel Clock Edge Select:
0: Parallel Interface Data is strobed on the Falling Clock
Edge.
1: Parallel Interface Data is strobed on the Rising Clock
Edge.
Reserved.
I
= 6.25 MHz / Register value (in decimal) 0x40'h = ~100
kHz SCL (default)
Note: Register values <0x32'h are NOT supported.
Deserializer Device ID = 0x60
(1100_000X) default
Reserved.
Slave Device ID. Sets remote slave I2C address.
Reserved.
Reserved.
Reserved.
Reserved.
2
2
DDIO
C Pass-Through Mode
C SCL frequency is determined by the following: f
voltage set
DDIO
detect
2
C Device ID overrides CAD
DDIO
by register.
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