DS92LX2121SQE National Semiconductor, DS92LX2121SQE Datasheet - Page 36

• Manufacturer Part Number: DS92LX2121SQE
• Description: SERDES, 10-50MHZ, 40LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX2121SQE

• Data Rate: 1.05Gbps
• No. Of Inputs: 21
• No. Of Outputs: 1
• Supply Voltage Range: 1.71V To 1.89V
• Driver Case Style: LLP
• No. Of Pins: 40
• Base Number: 2121
• Operating Temperature Range: -40°C To +85°C
• Serdes Function: Serializer
• Ic Input Type: LVCMOS
• Ic Output Type: LVCMOS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used over a wide variety
of balanced cables depending on distance and signal quality
requirements. The Ser/Des employ internal termination pro-
viding a clean signaling environment. The interconnect for
Channel Link III interface should present a differential
impedance of 100 Ohms. Use of cables and connectors that
have
impedance discontinuities. Shielded or un-shielded cables
may be used depending upon the noise environment and ap-
plication requirements. The chipset's optimum cable drive
performance is achieved at 43 MHz at 10 meters length. The
maximum signaling rate increases as the cable length de-
creases. Therefore, the chipset supports 50 MHz at shorter
distances. Other cable parameters that may limit the cable's
performance boundaries are: cable attenuation, near-end
crosstalk and pair-to-pair skew.
For obtaining optimal performance the system should use:
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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices
should be designed to provide low-noise power feed to the
device. Good layout practice will also separate high frequency
or high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (2
to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with
low-inductance parasitics, which has proven especially effec-
tive at high frequencies, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum elec-
trolytic types. RF capacitors may use values in the range of
0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF
to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
Shielded Twisted Pair (STP) cable
100Ω differential impedance and 24 AWG (or lower AWG)
cable
Low skew, impedance matched
Terminate unused conductors
matched
differential
impedance
will
minimize
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ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power for different portions
of the circuit. This is done to isolate switching noise effects
between different sections of the circuit. Separate planes on
the PCB are typically not required. Pin Description tables typ-
ically provide guidance on which circuit blocks are connected
to which power pin pairs. In some cases, an external filter
many be used to provide clean power to sensitive circuits
such as PLLs.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the differential lines to
prevent coupling from the LVCMOS lines to the differential
lines. Closely-coupled differential lines of 100 Ohms are typ-
ically recommended for differential interconnect. The closely
coupled lines help to ensure that coupled noise will appear as
common-mode and thus is rejected by the receivers. The
tightly coupled lines will also radiate less.
Information on the LLP style package is provided in National
Application Note: AN-1187.
INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
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Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
— S = space between the pair
— 2S = space between pairs
— 3S = space to LVCMOS signal
Minimize the number of Vias
Use differential connectors when operating above
500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair