PIC18F6723-E/PT Microchip Technology, PIC18F6723-E/PT Datasheet - Page 38

• Manufacturer Part Number: PIC18F6723-E/PT
• Description: PIC18 With 128KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6723-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F8723 FAMILY
2.4
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the T
ing the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D F
be selected. If the ACQT2:ACQT0 bits are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
DS39894B-page 38
Operation in Power-Managed
Modes
AD
time for the new clock speed. After enter-
RC
clock to
2.5
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (V
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
2: Analog levels on any pin defined as a dig-
Configuring Analog Port Pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
OH
or V
OL
© 2009 Microchip Technology Inc.
) will be converted.