PIC18F6723-E/PT Microchip Technology, PIC18F6723-E/PT Datasheet - Page 40

• Manufacturer Part Number: PIC18F6723-E/PT
• Description: PIC18 With 128KB Flash, 4KB RAM, 1024 DataEE, 12-bit ADC 64 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6723-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F8723 FAMILY
2.8
An A/D conversion can be started by the Special Event
Trigger of the ECCP2 module. This requires that the
CCP2M3:CCP2M0
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion, and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
software overhead (moving ADRESH:ADRESL to the
TABLE 2-2:
DS39894B-page 40
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
TRISA
TRISF
TRISH
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
2:
3:
(2)
Use of the ECCP2 Trigger
PORTA<7:6> and their direction bits are individually configured as port pins based on various primary
oscillator modes. When disabled, these bits read as ‘0’.
These registers are not implemented on PIC18F6628/6723 devices.
For these Reset values, see the “PIC18F8722 Family Data Sheet” (DS39646).
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register High Byte
A/D Result Register Low Byte
TRISA7
OSCFIF
OSCFIE
OSCFIP
TRISH7
TRISF7
PSPIF
PSPIE
PSPIP
ADFM
Bit 7
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(1)
bits
TRISA6
TRISH6
TRISF6
CMIE
CMIP
CMIF
ADIF
ADIE
ADIP
Bit 6
—
—
—
(CCP2CON<3:0>)
(1)
TRISA5
TRISH5
VCFG1
ACQT2
TRISF5
RC1IE
RC1IP
RC1IF
CHS3
Bit 5
—
—
—
TRISH4
TRISA4
TRISF4
VCFG0
ACQT1
INT0IE
TX1IE
TX1IP
TX1IF
CHS2
EEIF
EEIE
EEIP
Bit 4
be
TRISH3
SSP1IF
SSP1IE
SSP1IP
BCL1IF
BCL1IE
BCL1IP
TRISA3
TRISF3
PCFG3
ACQT0
CHS1
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
Special Event Trigger will be ignored by the A/D module
but will still reset the Timer1 (or Timer3) counter.
RBIE
Bit 3
ACQ
time selected before the Special Event Trigger
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISH2
HLVDIF
HLVDIE
HLVDIP
TRISA2
TRISF2
PCFG2
ADCS2
CHS0
Bit 2
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
TRISH1
TRISA1
TRISF1
PCFG1
ADCS1
INT0IF
Bit 1
© 2009 Microchip Technology Inc.
TMR1IF
TMR1IE
TMR1IP
CCP2IF
CCP2IE
CCP2IP
TRISH0
TRISA0
TRISF0
PCFG0
ADCS0
ADON
RBIF
Bit 0
Values
Reset
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)