PIC18F67J50T-I/PT Microchip Technology, PIC18F67J50T-I/PT Datasheet - Page 42
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J50T-I/PT
Manufacturer Part Number
PIC18F67J50T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F65J50-IPT.pdf
(480 pages)
3.PIC18F65J50-IPT.pdf
(16 pages)
Specifications of PIC18F67J50T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3904 B
Interface Type
I2C, MSSP, SPI, EUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
49
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183022, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Height
1 mm
Length
10 mm
Supply Voltage (max)
2.75 V, 3.6 V, 3.9 V
Supply Voltage (min)
1.7 V, 2 V, 3 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18F67J50T-I/PTTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J50T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87J50 FAMILY
2.4
Like
PIC18F87J10 family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F87J10 family devices offer two alternate clock
sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary clock sources include the External
Crystal and Resonator modes, the External Clock
modes and the internal oscillator block. The particular
mode is defined by the FOSC2:FOSC0 Configuration
bits. The details of these modes are covered earlier in
this chapter.
The secondary oscillators are those external sources
not connected to the OSC1 or OSC2 pins. These
sources may continue to operate even after the
controller is placed in a power-managed mode.
PIC18F87J10 family devices offer the Timer1 oscillator
as a secondary oscillator. This oscillator, in all
power-managed modes, is often the time base for
functions such as a Real-Time Clock (RTC). Most
often, a 32.768 kHz watch crystal is connected
between the RC0/T1OSO/T13CKI and RC1/T1OSI/
ECCP2/P2A pins. Like the HS Oscillator mode circuits,
loading capacitors are also connected from each pin to
ground. The Timer1 oscillator is discussed in greater
detail in Section 13.3 “Timer1 Oscillator”.
In addition to being a primary clock source, the
postscaled
power-managed mode clock source. The INTRC
source is also used as the clock source for several
special features, such as the WDT and Fail-Safe Clock
Monitor.
DS39775C-page 42
previous
Clock Sources and Oscillator
Switching
internal
PIC18
clock
enhanced
is
available
devices,
as
the
a
supplying the device clock, changing the states of these
frequency of the INTOSC postscaler is set at 4 MHz.
providing the device clock in secondary clock modes. In
2.4.1
The OSCCON register (Register 2-2) controls several
aspects of the device clock’s operation, both in
full-power operation and in power-managed modes.
The System Clock Select bits, SCS1:SCS0, select the
clock source. The available clock sources are the
primary clock (defined by the FOSC2:FOSC0 Configu-
ration bits), the secondary clock (Timer1 oscillator) and
the postscaled internal clock.The clock source changes
immediately, after one or more of the bits is written to,
following a brief clock transition interval. The SCS bits
are cleared on all forms of Reset.
The
IRCF2:IRCF0, select the frequency output provided on
the postscaled internal clock line. The choices are the
INTRC source, the INTOSC source (8 MHz) or one of
the frequencies derived from the INTOSC postscaler
(31 kHz to 4 MHz). If the postscaled internal clock is
bits will have an immediate change on the internal oscil-
lator’s output. On device Resets, the default output
When an output frequency of 31 kHz is selected
(IRCF2:IRCF0 = 000), users may choose which inter-
nal oscillator acts as the source. This is done with the
INTSRC bit in the OSCTUNE register (OSCTUNE<7>).
Setting this bit selects INTOSC as a 31.25 kHz clock
source by enabling the divide-by-256 output of the
INTOSC postscaler. Clearing INTSRC selects INTRC
(nominally 31 kHz) as the clock source.
This option allows users to select the tunable and more
precise INTOSC as a clock source, while maintaining
power savings with a very low clock speed. Regardless
of the setting of INTSRC, INTRC always remains the
clock source for features such as the Watchdog Timer
and the Fail-Safe Clock Monitor.
The OSTS and T1RUN bits indicate which clock source
is currently providing the device clock. The OSTS bit
indicates that the Oscillator Start-up Timer (OST) has
timed out and the primary clock is providing the device
clock in primary clock modes. The T1RUN bit
(T1CON<6>) indicates when the Timer1 oscillator is
power-managed modes, only one of these bits will be set
at any time. If none of these bits are set, the INTRC is
providing the clock or the internal oscillator block has just
started and is not yet stable.
The IDLEN bit determines if the device goes into Sleep
mode, or one of the Idle modes, when the SLEEP
instruction is executed.
Internal
OSCILLATOR CONTROL REGISTER
Oscillator
© 2009 Microchip Technology Inc.
Frequency
Select
bits,
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