SST25VF040B-80-4I-SAE-T Microchip Technology, SST25VF040B-80-4I-SAE-T Datasheet - Page 19

2.7V To 3.6V 4Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R

SST25VF040B-80-4I-SAE-T

Manufacturer Part Number
SST25VF040B-80-4I-SAE-T
Description
2.7V To 3.6V 4Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
Manufacturer
Microchip Technology

Specifications of SST25VF040B-80-4I-SAE-T

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
4M (512K x 8)
Speed
80MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
4 Mbit SPI Serial Flash
SST25VF040B
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status regis-
ter. CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
19 for EWSR or WREN and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to “1”. When
the WP# is low, the BPL bit can only be set from “0” to “1” to
lock-down the status register, but cannot be reset from “1”
to “0”. When WP# is high, the lock-down function of the
©2009 Silicon Storage Technology, Inc.
FIGURE 19: Enable-Write-Status-Register (EWSR) or
SCK
CE#
SO
SI
Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
MODE 3
MODE 0
0 1 2 3 4 5 6 7
MSB
50 or 06
HIGH IMPEDANCE
MODE 3
MODE 0
19
MSB
BPL bit is disabled and the BPL, BP0, and BP1 and BP2
bits in the status register can all be changed. As long as
BPL bit is set to 0 or WP# pin is driven high (V
low-to-high transition of the CE# pin at the end of the
WRSR instruction, the bits in the status register can all be
altered by the WRSR instruction. In this case, a single
WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0, BP1, and
BP2 bits at the same time. See Table 2 for a summary
description of WP# and BPL functions.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
01
MSB
7 6 5 4 3 2 1 0
REGISTER IN
STATUS
1295 EWSR.0
S71295-05-000
IH
Data Sheet
) prior to the
10/09

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