XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet

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... The XR88C681 device offers a single IC solution for the 8080/85, 8086/88, Z80, Z8000, 68xx and 65xx microprocessor families. ORDERING INFORMATION Part No. XR88C681CJ XR88C681CN/40 XR88C681CP/28 XR88C681CP/40 XR88C681J XR88C681N/40 XR88C681P/28 XR88C681P/40 Rev. 2.11 E2006 D Programmable Interrupt Daisy Chain D 8 General Purpose Outputs (40 Pin DIP and 44 Pin ...

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TXDA RXDA TXDB TSR RSR TSR THR RHR THR Mode Registers Mode Registers Status Register Channel A Operation Control CRB CRA Data Bus Command Decoder Buffer Address Decoder -RD -WR -CS RESET Figure 1. ...

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PIN CONFIGURATION A3 7 IP0 8 -WR 9 -RD 10 RXDB 11 NC XR-68C681CJ 12 PLCC TXDB 13 14 OP1 OP3 15 OP5 16 OP7 17 44 Lead PLCC Rev. 2. -RESET X1/CLK 35 ...

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PIN DESCRIPTION 44 PLCC 40 PDIP, 28 PDIP CDIP ...

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PLCC 40 PDIP, 28 PDIP CDIP ...

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PLCC 40 PDIP, 28 PDIP CDIP Rev. 2.11 Symbol Type Description OP4 O Output 4 (General Purpose Output). This ...

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PLCC 40 PDIP, 28 PDIP CDIP Rev. 2.11 Symbol Type Description RESET I Master Reset ...

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DC ELECTRICAL CHARACTERISTICS Test Conditions 70° Symbol Parameter V Input Low Voltage IL V Input High Voltage IH V Input High Voltage (Military Input High Voltage (X1/CLK) IHX1 V Output Low Voltage ...

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AC ELECTRICAL CHARACTERISTICS Test Conditions 70° Symbol Parameter Reset Timing (See Figure 51) t RESET Pulse Width RES XR88C681 Read and Write Cycle Timing (Figure 52) t A0-A3 Setup Time to RD ...

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Symbol Parameter t X1/CLK (External) High or Low CLK Time t X1/CLK Crystal or External CLK Frequency Rev. 2.11 Min. Typ. Max. Unit 100 ns 7.372 MHz 10 Conditions ...

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AC ELECTRICAL CHARACTERISTICS Test Conditions 70° Symbol Parameter Clock Timing (Figure 56) (Cont’d.) t Counter/Timer External Clock CTC High or Low Time (IP2) t Counter/Timer External Clock CTC Frequency t RXCn and TXCn (External) ...

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This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive stat- ic charge. Nonetheless suggested that conventional precautions be taken to avoid applying any voltage larger than the rated ...

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SYSTEM DESCRIPTION The XR88C681 consists of two independent, full-duplex communication channels; each consisting of their own Transmitter and Receiver. Each channel of the DUART may be independently programmed for operating mode and data format. The DUART can interface to a ...

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E clock -RESET Figure 2. External Logic Circuitry required to interface a 6800 Family B.1 DUART Register Addressing The addressing of the internal registers of the DUART is presented in Table 1. Please note that some of the registers ...

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Address (Hex) Register Name 00 Mode Register, Channel A 01 Status Register, Channel A 02 Masked Interrupt Status Register 03 Rx Holding Register, Channel A 04 Input Port Change Register 05 Interrupt Status Register 06 Counter/Timer Upper Byte Register 07 ...

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Command Register. Therefore, both Mode Registers, within a given channel, have the same logical address. The features and functions of the DUART that are controlled by the Mode Registers are discussed in detail in ...

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Bit 7 Bit Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Rev. 2.11 Bit 5 Bit 4 Description 0 0 Reset ...

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Bit 7 Bit Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, In addition to the commands which are available through the command registers, the DUART also offers “Address-Triggered” commands. ...

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C. INTERRUPT CONTROL BLOCK The Interrupt Control Block allows the user to apply the DUART in an “Interrupt Driven” environment. DUART includes an interrupt request output signal ( INTR), which may be programmed to be asserted upon - the occurrence ...

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Write a logic “1” to IMR[7]. ISR[6] Delta Break Indicator - Channel B When this bit is set, it indicates that the Channel B receiver has detected the beginning or end of a received break (RB). This bit is ...

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RHRA, following data reception. Hence possible that the last two char- acters in a string of data (being received) could be lost due to this phenomenon. Therefore, the user is ...

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Receiver problems such as Parity Error (PE), Receiver Overrun Error (OE), or Framing Error (FE). The DUART also does not offer the user to ability to configure one of the output ports to relay the occurrence of any of these ...

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For CPUs that employ direct interrupts, this “location” is fixed by the CPU circuitry itself. For Example: If the INT0 interrupt request input pin, of the 8051 asserted, ...

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C.6.1.1 8051 Microcontroller The 8051 family of microcontrollers is manufactured by Intel and comes with a variety of amenities. Some of these amenities include chip serial port D Four 8 bit I/O port (P0 - P3) D Two ...

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P3.0 (RXD) P3.1 (TXD) P3.2 (-INT0) P3.3 (-INT1) P3.4 (T0) P3.5 (T1) P3.6 (-WR) P3.7 (-RD) The 8051 C consists of 4 8-bit I/O ports. Some of these ports have alternate functions, as will be discussed here. Port 0 (P0.0 ...

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Port 3 Port dual-purpose port on pins 10 - 17. In addition to functioning as general purpose I/O, these pins have multiple functions. Each of these pins have an alternate purpose, as listed in Table 8. Bit ...

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PORT 0 (AD0 - AD7) ALE PORT 2 (A8 - A15) 8051 CPU Figure 5. An Approach to Interfacing the XR88C681 DUART to the 8051 Microcontroller The circuitry presented Figure 5 would function as follows during a ...

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CPU, from a external crystal. Controller is responsible for buffering the bi-directional Data Bus. Additionally, since the 8080 CPU device does not directly provide control bus signals, the 8228 Device is responsible for translating signaling information, from the 8080A device, ...

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Hence, when -INTA is asserted, the CPU module is awaiting “vector” information on the Data bus. In the case of the 8080A CPU Module, this “vector” information is typically the op-code for one of the RESTART instructions (RST). ...

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U1 INTE INT DBIN 8080A CPU Figure 7. Circuit Schematic depicting approach to Interface the XR88C681 DUART to the 8080A CPU, for “External” Vectored Interrupt Processing (Interrupt Service Routine resides at 0020 ...

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Figure 8 presents a schematic of the 8085 CPU Module. AD0 AD1 AD2 AD3 AD4 AD5 X1 AD6 AD7 X2 TRAP RST 7.5 RST 6.5 RST 5.5 INTR - INTA ALE A8 A9 A10 A11 A12 A13 A14 A15 - ...

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AD0 - AD7 X1 ALE X2 TRAP RST 7.5 RST 6.5 RST 5.5 INTR - INTA A8 - A15 - IO 8085 CPU Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory ...

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Input Name Trigger RST 7.5 Positive Edge Triggered RST 6.5 High Level Until Sampled RST 5.5 High Level Until Sampled INTR High Level Until Sampled Table 11. 8085 CPU Maskable Interrupt Request Inputs and their Features Direct Interrupts The 8085 ...

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RST 6.5 AD0 - AD7 ALE A15 - A8 -IO/M -RD -WR 8085 CPU Figure 10. The XR88C681/8085 CPU Interface for Direct Interrupt Processing (Interrupt Service Routine is located at 0034 Figure 11 presents a schematic where the DUART will ...

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U1 INTR -INTA 8085 CPU AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE Figure 11. The XR88C681/8085 CPU Interface for Vectored Interrupt Processing (In- terrupt Service Routine is located at 0020 C.6.1.4 68HC11 Microcontroller Motorola manufactures a family of ...

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Figure 12 presents the block diagram of the MC68HC11 C. MODA MODB Mode Control Timer System Port A Figure 12. Block Diagram of the MC68HC11 Microcontroller The 68HC11 can be configured to operate in a “Single Chip” Mode or in ...

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Accumulator. Three of the input pins support input capture functions; and four of the output pins support output compare functions. Port B Port B consists of 8 output pins. If the 68HC11 C is operating in the single chip mode, ...

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E -R/W MODA A8 - A15 MODB -IRQ AS AD0 - AD7 68HC11 Figure 13. XR88C681/MC68HC11 Microcontroller Interfacing Approach Rev. 2.11 Address Decoder 74HC373 38 to other ICs -CS -RD ...

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E clock -RESET Figure 14. Glue Logic Circuitry Required to Interface the MC68HC11 C to the XR88C681 DUART C.6.1.5 Z-80 CPU The Z-80 CPU can be interfaced to a DUART operating in the I-Mode (the CPU) is ...

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V CC -INT V CC CPU -IACK Figure 15. A Diagram of Numerous DUARTs Configured in an Interrupt In addition to the INTR and IACK pins, the Z-Mode - - DUART also uses the IEI and IEO pins; which are ...

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CPU. This “lower priority” DUART will be prohibited from issuing interrupts until the IEO pin of the “highest priority” DUART has toggled “high”. Referring, once again, to Figure 15, the further to the ...

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Z-80 P can be configured to operate in one of three different “interrupt modes”. The Z-80 is also a little bit less complicated to interface to (than some of the P/ Cs The Z-80 CPU will support Read/Write operations between ...

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GND +5V Clock input PHI -INT -NMI -WAIT -BUSRQ -HALT -RFSH -BUSAK -RESET Figure 18. Schematic of Z-80 CPU Module Z-80 CPU Interrupt Servicing Capability The Z-80 CPU contains two interrupt request pins: and INT. NMI is the “Non-Maskable” interrupt ...

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Data Bus, following the assertion of INTA. In this case (for this interrupt - mode), this “vector” information is the op-code for one of the RESTART instructions (RST). supports up to eight different RST instructions ...

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INTR output. This action will, in turn, cause the - of the CPU to be asserted. Once the CPU has completed its current instruction, the CPU Module will assert the INTA signal. This will in turn assert the - Acknowledge) ...

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C.6.2.2 8086 Microprocessor The 8086 microprocessor bit microprocessor manufactured by Intel Corporation. Figure 20 presents the pin out diagram of this IC. Please note that in Figure 20, pins have some additional labels, located ...

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AD0 - AD15 becomes D0 - D15, A16/S3 - A19/S6 becomes S3 - S6). A second group of multiplexed pins is controlled by the MN/ MX input pin. When this pin is high, - the “min” mode is selected ...

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Figure 21 and Figure 22 present the 8086 CPU Mode, when operating in the “min” and “max” modes, respectively. INTR -INTA HOLD -DEN DT/-R Vcc MN/-MX 8086 CPU Figure 21. Schematic of the 8086 CPU Mode (Min Mode) Rev. 2.11 ...

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CLK INTR 8086 CPU MN/-MX Figure 22. Schematic of the 8086 CPU Mode (Max Mode) 8086 C Interrupt Processing If a peripheral component requires interrupt service from the CPU, it will assert the CPU’s INTR input (by toggling it high). ...

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AD0 - AD7 AD8 - AD15 HOLD ALE - INTA - DEN INTR - DT MN 8086 CPU Figure 23. Schematic of the XR88C681 DUART Device Interfacing to ...

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TXCA TXCB IP2 Divide by 16 ACR[4-6] X1/CLK Oscillator Circuit X2 Figure 24. Block Diagram of DUART Timing Control Block Each element of the Timing Control Block is discussed here: D.1 Oscillator Circuit: A crystal oscillator is typically connected externally ...

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C1 C2 Figure 25. A Recommended Schematic for the XTAL Oscillator Circuitry Note: The user also has an option to drive the Oscillator Circuit with a TTL input signal, in lieu of using a crystal oscillator. If this approach is ...

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D.2 Bit Rate Generator The BRG (Bit Rate Generator) accepts the timing output of the Oscillator Circuit and generate the clock signal for 23 commonly used data communication bit rates ranging from 50 bps up to 115.2kbps. Please note that ...

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D.3 Counter/Timer The Timing Control Block also contains a 16 bit Counter/Timer (C/T). The C programmable 16 bit down-counter which can use one of several timing sources as its input. Figure 28 presents a block diagram of the ...

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D.3.1 Timer Mode: Please note that of the two C/T Modes, the Timer Mode is the only mode which is relevant to the function of Bit Rate Selection. However, for completeness, the Counter Mode is also discussed here. In the ...

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Receivers. Table 17 and Table 18 present the relationship between the contents of the CSRs and the clock source driving the Transmitters and Receivers. Bit 7 Bit 6 Receiver Clock Select See Table 18 Table 17. Bit Format of ...

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Register Command Register A, CRA Command Register A, CRA Command Register B, CRB Command Register B, CRB Table 19. Command Register Controls Over the Extend Bit Note: If the user programs either nibble of the Clock Select Register (CSRn[7:4] or ...

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Figure 30. Receiver (1X) Sampling, if the RX Clock is Slightly Faster Than the TX Clock Figure 30 shows that the phase relationship between the Receiver’s sampling point and each serial data bit is changing. In this case, the Receiver ...

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In general the bit-error-rate, for this “uncorrected” system is a function of the timing differences between the TX and RX local clock signals. However, in order to correct for Receiver Drift and to minimize the BER during serial data transmission, ...

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The oversampling technique mitigates many of the serial data bit errors by attempting to adjust the receiver sampling point, to near the midpoint of the bit periods character to character basis. This approach is successful for two reasons: ...

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Externally connect the OP3 pin to the IP3 and IP4 pins. Thereby applying a 1 MHz square wave into these two input pins. 3. Write FF to CSRA. 16 This step will specify that the timing source for the ...

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This spec is not related to the parameter tRTX, which also specifies limits on signals applied to IP2 or other input pins, for use at the External Clock Source for Transmitter and Receivers RXC and TXC (External) ...

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Input Port Alternate Function(s) - IP0 CTSA: Clear to Send (CTS) input for Channel A. Note: this input is Active Low, for the CTS function - IP1 CTSB: Clear to Send (CTS) input for Channel B. Note: This input is ...

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In order to enable the “Input Port Change of State” interrupt, one must do the following. D Write the appropriate data to the lower nibble of ACR. The bit formats for ACR is presented in Table 23. Please note that ...

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Data Bus, specifying the bits, within the OPR set ( 1 = set change). A bit is cleared by the address triggered “CLEAR OUTPUT PORT BITS” command (see Table 1) with the ...

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In summary, for the “SET OUTPUT PORT BITS” command results in no change for OPR[n], nor Output Port pin OPn results in OPR[n] = “1”, and Output Port pin, OPn = “0” F.1.2 Clear ...

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F.2 Output Port Configuration Register (OPCR) The Output Port pins can be used as General Purpose Output pins, or they can be configured to used in alternate functions. Table 24 lists the Alternate Functions of each of the Output Port ...

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F.3 28 Pin DIP Packaged DUARTs The 28 pin DIP packaged devices have only two output ports, OP0 and OP1. Hence the effect of the “SET OUTPUT PORT BITS” and “CLEAR OUTPUT PORT BITS” commands only effects these two pins. ...

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Whenever a transmitter is idle or inactive, the TXDn output for that particular channel will be continuously marking (at a logic “high”). However, just prior to the transmission of a character, the transmitter alerts the receiver by generating a “START” ...

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Receive Shift Register RXDn Incoming Serial Data Figure 37. A Simplified Drawing of the Receiver Shift Register The receiver functions by sensing the voltage level at the RXDn input. When the far-end transmitter is idle, its TXDn output (and consequently, ...

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Receiver Errors If the Receiver does not sample a “mark”, at the presumed time of the STOP bit, a Framing Error (FE) is flagged by setting, SRn[6] =1. If, upon complete reception of the character, the subsequent parity check is ...

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Bit 7 Bit 6 Channel Mode Tx RTS Control 00 = Normal 01 = Auto Echo 10 = Local Loop 11 = Remote Loop MR1n[7] - Receiver Request to Send Control Ordinarily, RTS (Request to Send) is asserted or negated ...

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MR2n[7:6] - Channel Mode Select Each Channel can operate in one of four modes. D Setting MR2n[7: configures the channel to op- erate in the Normal Mode. In this mode, the receiver and transmitter operate independently. presents a ...

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RXDn Incoming Receive Shift Register Serial Data Receive Holding Register To Data Bus (To be read by the CPU) Figure 39. A Block Diagram Depict Automatic Echo Mode In this mode: 1. Received data is transmitted on the channel’s TXD ...

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Receive Shift Register RXDn Receive Holding Register To Data Bus (To be read by the CPU) Figure 40. A Block Diagram depicting Local Loopback Mode Operation In this mode: 1. The transmitter output is internally connected to the receiver input. ...

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RXDn Incoming Receive Shift Register Serial Data Receive Holding Register Note: The CPU has no access to the Serial Data during Remote Loopback Mode. Figure 41. A Block Diagram Depicting Remote Loopback Mode In this mode: 1. Received data is ...

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MR2n[3:0] - Stop Bit Length This bit field programs the duration of the stop bits appended to each transmitted character. duration of 9/ bit time and 1 9/ bit times, in increments of 1/16 bits can ...

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STOP bit is properly detected in the next character. If the “Error” Mode has been set to “Block” mode, then this bit, once set will remain ...

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H. SPECIAL MODES OF OPERATION H.1 RTS/CTS Handshaking The DUART can be programmed to support RTS/CTS Handshaking means of data flow control with other devices. This section will describe a couple of options that the DUART allows the ...

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Figure 42 shows two DUART devices, a “Receiving Device” and a “Transmitting Device”. These devices are labeled such because of their role in this example transfer of data between them. This example is going to ignore, for the time being, ...

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Assert RTSA Write 01h to QUART Address 0Eh (This invokes the “SET OUTPUT PORT BITS COMMAND” and sets the Output Port pin, OP0 to a logic No Figure 43. A Flow Diagram Depicting an Algorithm That Could be Used to ...

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Transmitting Device TXRDY_A (OP7) To CPU TXRDY_A RTSA CTSA RXDA Figure 44. Block Diagram and Timing Sequence of Two DUARTs Connected in the Transmitter-RTS Controlled Configuration. Rev. 2.11 RTSA (OP0) CTSA (IP0) TXDA 82 Receiving Device IP2 (RTS-in) OP3 (CTS-out) ...

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Figure 44 shows two DUART devices, one labeled “Transmitting Device” and the other, “Receiving Device”. This example starts with the assumption that the “Transmitter Device” has been programmed such that MR2A[ which results in programming the “Transmitting Device” ...

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START ASSERT RTSA (Write 01h to DUART Address 0Eh) *CTSA INPUT IS ASSERTED. Data transmission is now permitted. Is TXEMT Asserted ? *RTSA is Automatically Negated by Receiver Controlled RTS Function. (OP0 toggles “High”) -CTSA INPUT IS NEGATED. Data transmission ...

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RXDn 00h Figure 46. An Illustration Depicting the Concept of Multi-Drop Mode LSB Figure 47. Bit Format of Character Data Being Transmitted in the Multi-Drop Mode The “Master Station” communicates to the “Slave Stations” by transmitting a character (typically a ...

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An Address Byte, however, interrupts all “Slaves” so that each can examine the received byte to test if it (the individual slave device) is being addressed. The receiver of the addressed slave will be enabled and will prepare for reception ...

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Receiver Operation During Multi-Drop Mode When a channel has been programmed into the Multi-Drop Mode, and the Receiver has been disabled (a typical configuration), the Receiver will load a character into the RHR and set the RXRDY indicator (and/or interrupt) ...

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H.3 Standby Mode The DUART may be placed in a standby mode to conserve power when its operation is not required. Upon reset, the DUART will be in the “ACTIVE OPERATION” mode. A “SET STANDBY MODE” command issued via the ...

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Bit 7 Bit 6 Bit 5 Channel Mode Tx RTS Control 00 = Normal Auto Echo 1 = Yes 10 = Local Loop 11 = Remote Loop Bit 7 Bit 6 Bit 5 Receiver Clock ...

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Bit 7 Bit 6 Bit 5 BRG Set Counter/Timer #1 Mode and Source Select 0 = Set1 See Table Set2 Bit 7 Bit 6 Bit 5 Delta IP3 Delta IP2 Delta IP1 ...

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K. TIMING DIAGRAMS 4.0V Figure 50. Input and Output Levels for Timing Measurements Note: AC testing inputs are driven at 0.4V for a logic “0” and 2.4V for a logic “1” except for -40 to 85(C and -55 to 125(C, ...

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- - FLOAT (Read) - (Write) Figure 52. XR88C681 Read and Write Cycle Timing Rev. 2. RWD ...

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IAS - FLOAT IEI t DIO t EOD IEO t DIO Figure 53. XR88C681 Z Mode Interrupt Cycle Timing Rev. 2. EIS NOT VECTOR VALID 93 XR88C681 ...

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PS IP0 - IP6 -WR or -CS OP0 - OP7 -RD or -CS or -WR Interrupt Output Rev. 2. OLD DATA t PD Figure 54. Port Timing t IR Figure 55. Interrupt Timing 94 ...

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C1: 10pF + (Stray < 5pF) C2: 10pF + (Stray < 5pF) R1: 100ohm R2: 100ohm C1 C2 3.6864MHz Parallel Resonant Crystal X1/CLK C/T CLK RXC TXC Rev. 2. XR88C681 CLK t CTC t RTX ...

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TXC (Input) t TXD TXD TXC (1X Output) RXC 1X Input) RXD Rev. 2.11 1 Bit Time ( Clocks) t TCS Figure 57. Transmitter Timing t t RXS RXH Figure 58. Receiver Timing 96 ...

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LEAD PLASTIC LEADED CHIP CARRIER SYMBOL Note: The control dimension ...

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LEAD CERAMIC DUAL-IN-LINE Base 1 Plane Seating L Plane B SYMBOL Note: The control dimension is the inch column Rev. 2.11 (600 MIL CDIP) Rev. ...

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LEAD PLASTIC DUAL-IN-LINE Seating Plane L B SYMBOL Note: The control dimension is the inch column ...

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A Seating Plane L B Rev. 2.11 40 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1. INCHES SYMBOL MIN MAX A 0.160 0.250 A 0.015 0.070 1 A 0.125 0.195 2 B 0.014 0.024 B 0.030 ...

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... While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized ...