XRT7295ATIW Exar Corporation, XRT7295ATIW Datasheet - Page 14

• Manufacturer Part Number: XRT7295ATIW
• Description: DS3/SONET STS-1 Line Receiver
• Manufacturer: Exar Corporation

Specifications of XRT7295ATIW

• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

TIMING CHARACTERISTICS
Test Conditions: All Timing Characteristics are Measrured with 10pF Loading, -40°C ± T
5V ±10%
BOARD LAYOUT CONSIDERATIONS
Power Supply Bypassing
Figure 12 illustrates the recommended power supply
bypassing network. A 0.1mF capacitor bypasses the
digital supplies. The analog supply V
using a 0.1mF capacitor and a shield bead that removes
significant amounts of high-frequency noise generated by
the system and by the device logic.
high-frequency (low lead inductance) capacitors should
be used. Finally, it is most important that all ground
connections be made to a low-impedance ground plane.
Receive Input
The connections to the receive input pin, R
carefully considered. Noise-coupling must be minimized
along the path from the signal entering the board to the
tRCH1RCH2
tRCL2RCL1
Rev.1.20
tRCHRDV
RPDATA
RNDATA
Symbol
RCLK
(RD)
OR
(RC)
Parameter
Clock Rise Time (10% - 90%)
Clock Fall Time (10% - 90%)
Receive Propagation Delay
Clock Duty Cycle
tRCHRDV
Figure 11. Timing Diagram for System Interface
Table 7. System Interface Timing Characteristics
tRDVRCL
DD
A is bypassed by
Good quality,
IN
, must be
1
14
input pin. Any noise coupled into the XRT7295AT input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.
PLL Filter Capacitor
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible. The LPF1
and LPF2 pins are adjacent, allowing for short lead
lengths with no crossovers to the external capacitor.
Noise-coupling into the LPF1 and LPF2 pins may
degrade PLL performance.
Handling Precautions
Although protection circuitry has been designed into this
device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during
handling and mounting.
tRCL2RCL1
tRCLRDX
Min
0.6
45
Typ
50
Max
3.7
55
tRCH1RCH2
4
4
A
± +85°C, V
Unit
ns
ns
ns
%
DD
=