GD82551IT Intel, GD82551IT Datasheet - Page 15

• Manufacturer Part Number: GD82551IT
• Manufacturer: Intel

Specifications of GD82551IT

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Lead Free Status / RoHS Status: Not Compliant

4.2.3
Datasheet
Table 4.
Table 5.
Interface Control Signals
System and Power Management Signals
System and Power Management Signals
IDSEL
DEVSEL#
REQ#
GNT#
INTA#
SERR#
PERR#
CLK
CLK_RUN#
RST#
PME#
Symbol
Symbol
IN
STS
TS
IN
OD
OD
STS
IN
IN/OUT
OD
IN
OD
Type
Type
Initialization Device Select. The initialization device select signal is
used by the 82551IT as a chip select during PCI configuration read
and write transactions. This signal is provided by the host in PCI
systems.
Device Select. The device select signal is asserted by the target once
it has detected its address. As a bus master, the DEVSEL# is an input
signal to the 82551IT indicating whether any device on the bus has
been selected. As a bus slave, the 82551IT asserts DEVSEL# to
indicate that it has decoded its address as the target of the current
transaction.
Request. The request signal indicates to the bus arbiter that the
82551IT desires use of the bus. This is a point-to-point signal and
every bus master has its own REQ#.
Grant. The grant signal is asserted by the bus arbiter and indicates to
the 82551IT that access to the bus has been granted. This is a point-
to-point signal and every master has its own GNT#.
Interrupt A. The interrupt A signal is used to request an interrupt by
the 82551IT. This is an active low, level-triggered interrupt signal.
System Error. The system error signal is used to report address
parity errors. When an error is detected, SERR# is driven low for a
single PCI clock.
Parity Error. The parity error signal is used to report data parity errors
during all PCI transactions except a Special Cycle. The parity error pin
is asserted two clock cycles after the error was detected by the device
receiving data. The minimum duration of PERR# is one clock for each
data phase where an error is detected. A device cannot report a parity
error until it has claimed the access by asserting DEVSEL# and
completed a data phase.
Clock. The Clock signal provides the timing for all PCI transactions
and is an input signal to every PCI device. The 82551IT requires a PCI
Clock signal (frequency greater than or equal to 16 MHz) for nominal
operation. The 82551IT supports Clock signal suspension using the
Clockrun protocol.
Clockrun. The Clock Run signal is used by the system to pause or
slow down the PCI Clock signal. It is used by the 82551IT to enable or
disable suspension of the PCI Clock signal or restart of the PCI clock.
When the Clock Run signal is not used, this pin should be connected
to an external pull-down resistor.
Reset. The PCI Reset pin is used to place PCI registers, sequencers,
and signals into a consistent state. When RST# is asserted, the
82551IT ignores other PCI signals and all PCI output signals will be
tristated. The PCI Reset pin should be pulled high to the main digital
power supply.
Power Management Event. The Power Management Event signal
indicates that a power management event has occurred in a PCI bus
system.
Name and Function
Name and Function
Networking Silicon — 82551IT
9