GD82551IT Intel, GD82551IT Datasheet - Page 2

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GD82551IT

Manufacturer Part Number
GD82551IT
Description
Manufacturer
Intel
Datasheet

Specifications of GD82551IT

Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Lead Free Status / RoHS Status
Not Compliant
Revision History
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Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82551IT may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Revision Date
March 2008
Sept 2007
Sept 2007
April 2005
Sep 2004
Nov 2004
July 2005
Feb 2007
Nov 2008
Oct 2003
Jan 2005
Oct 2006
Revision
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
• Initial draft for release (non-classified).
• Added references to the MDI/MDI-X feature.
• Added lead-free information.
• Removed EEPROM Map bit descriptions. These descriptions can now be found in
• Added 82551IT Test Port Functionality (Chapter 10).
• Added new values for RBIAS100 and RBIAS10. RBIAS100 = 649 and RBIAS10
• Removed all references to the 82551ER and 82551QM controllers. 82551ER and
• Updated the section describing “Multiple Priority Transmit Queues”.
• Updated the section describing “VLAN Support”.
• Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to
• Added statement that no changes to existing soldering processes are needed for
• Added a note for PHY signals RBIAS100 and RBIAS10 to Table 8.
• Corrected the note in section 11stating that the maximum rating for the Case Tem-
• Corrected the X1 Clock Specifications for symbol Tx1_pr from ±50 ppm to ±30
• Added Figure 28 “196 PBGA Package Pad Detail”. The figure shows solder resist
• Updated section 11.1 “Absolute Maximum Ratings”.
• Added Section 13 “Reference Schematics”, updated Section 11.1 (changed Tcase
• Updated Figures 31 and 32. Added Digital I/O and Crystal Input One (X1) Charac-
• Updated Figure 32: changed TEST pull down resistor value (62 K to 1 K).
• Updated Table 12 (changed words 30h:33h to reserved).
• Updated Table 8 (X1 and X2 pin descriptions).
• Updated Tables 52 and 53 (Digital I/O and crystal input one (X1) characteristics).
the 82551QM/ER/IT EEPROM Map and Programming Information.
= 619 .
82551QM information can now be found in their respective datasheets.
a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pin-
out Information.
the 2-layer 0.32 mm wide-trace substrate change in the section describing “Pack-
age Information”.
perature under Stress for the 82551QM/ER is 70° C instead of 85° C.
ppm.
opening and metal diameter dimensions.
to ambient) and added ordering information to Section 1.4.
teristics (Tables 52 and 53). Updated Section 5.6.4.
Description
Datasheet

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