ISP1507ABSTM STEricsson, ISP1507ABSTM Datasheet - Page 36

• Manufacturer Part Number: ISP1507ABSTM
• Manufacturer: STEricsson

Specifications of ISP1507ABSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Table 18.
CD00222689
Product data sheet
Packet sequence High-speed
Transmit-Transmit
(host only)
Receive-Transmit
(host or
peripheral)
Receive-Receive
(peripheral only)
Transmit-Receive
(host or
peripheral)
Link decision times
9.8.1.2 Allowed link decision time
link delay
15 to 24
1 to 14
1
92
The amount of clock cycles allocated to the link to respond to a received packet and
correctly receive back-to-back packets is given in
values given in
packet sequences and timing are shown in
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1, Section 3.8.2.6.3.
Full-speed
link delay
7 to 18
7 to 18
1
80
Table 18
Low-speed
link delay
77 to 247
77 to 247
1
718
Rev. 04 — 20 May 2010
for correct USB system operation. Examples of high-speed
Definition
Number of clock cycles a host link must wait before driving
the TXCMD for the second packet.
In high-speed, the link starts counting from the assertion of
STP for the first packet.
In full-speed, the link starts counting from the RXCMD,
indicating LINESTATE has changed from SE0 to J for the
first packet. The timing given ensures inter-packet delays of
2 bit times to 6.5 bit times.
Number of clock cycles the link must wait before driving the
TXCMD for the transmit packet.
In high-speed, the link starts counting from the end of the
receive packet; deassertion of DIR or an RXCMD, indicating
RxActive is LOW.
In full-speed or low-speed, the link starts counting from the
RXCMD, indicating LINESTATE has changed from SE0 to J
for the receive packet. The timing given ensures inter-packet
delays of 2 bit times to 6.5 bit times.
Minimum number of clock cycles between consecutive
receive packets. The link must be able to receive both
packets.
Host or peripheral transmits a packet and will time-out after
this number of clock cycles if a response is not received. Any
subsequent transmission can occur after this time.
Figure 15
ISP1507A; ISP1507B
Table
and
18. Link designs must follow
ULPI HS USB OTG transceiver
Figure
16. For details, refer to
© ST-ERICSSON 2010. All rights reserved.
36 of 81