ISP1507ABSTM STEricsson, ISP1507ABSTM Datasheet - Page 54

• Manufacturer Part Number: ISP1507ABSTM
• Manufacturer: STEricsson

Specifications of ISP1507ABSTM

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

Table 31.
Table 32.
Table 33.
Table 34.
CD00222689
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
Symbol
-
ID_GND_R
SESS_END_R
SESS_VALID_R
VBUS_VALID_R
HOST_DISCON_
R
Symbol
-
ID_GND_F
SESS_END_F
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit allocation
USB_INTR_EN_R_E - USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh,
S = 0Eh, C = 0Fh) bit description
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit allocation
USB_INTR_EN_F_E - USB Interrupt Enable Falling Edge register (address R = 10h to 12h, W = 10h,
S = 11h, C = 12h) bit description
10.1.5 USB_INTR_EN_R_E register
10.1.6 USB_INTR_EN_F_E register
R/W/S/C
R/W/S/C
7
0
7
0
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 0 to logic 1. By default, all
transitions are enabled.
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB_INTR_STAT register change from logic 1 to logic 0. By default, all
transitions are enabled. See
Description
reserved
ID Ground Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on ID_GND.
Session End Fall: Enables interrupts and RXCMDs for logic 1 to logic 0 transitions on
SESS_END.
reserved
R/W/S/C
Description
reserved
ID Ground Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on ID_GND.
Session End Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_END.
Session Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
SESS_VLD.
V
A_VBUS_VLD.
Host Disconnect Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
HOST_DISCON.
reserved
R/W/S/C
BUS
6
0
6
0
Valid Rise: Enables interrupts and RXCMDs for logic 0 to logic 1 transitions on
R/W/S/C
R/W/S/C
5
0
5
0
Rev. 04 — 20 May 2010
Table 31
ID_GND_R
ID_GND_F
Table
R/W/S/C
R/W/S/C
4
1
4
1
shows the bit allocation of the register.
33.
R/W/S/C
R/W/S/C
END_R
END_F
SESS_
SESS_
3
1
3
1
ISP1507A; ISP1507B
VALID_R
VALID_F
R/W/S/C
R/W/S/C
SESS_
SESS_
ULPI HS USB OTG transceiver
2
1
2
1
VALID_R
R/W/S/C
VALID_F
R/W/S/C
VBUS_
VBUS_
© ST-ERICSSON 2010. All rights reserved.
1
1
1
1
DISCON_R
DISCON_F
R/W/S/C
R/W/S/C
HOST_
HOST_
0
1
0
1
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