CY7C68000-48BAC Cypress Semiconductor Corp, CY7C68000-48BAC Datasheet - Page 3

• Manufacturer Part Number: CY7C68000-48BAC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68000-48BAC

• Number Of Transceivers: 1
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Lead Free Status / RoHS Status: Not Compliant

1.0
The Cypress EZ-USB TX2 is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial/deserializer, to a parallel
interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The TX2 provides a high-speed physical layer interface that operates
at the maximum allowable USB 2.0 bandwidth. This allows the system designer to keep the complex high-speed analog USB
components external to the digital ASIC which decreases development time and associated risk. A standard interface is provided
that is USB 2.0-certified and is compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/01.
Two packages are defined for the family: 56-pin SSOP and 48-pin FBGA.
The function block diagram is shown in Figure 1-1.
Document #: 38-08016 Rev. *C
• UTMI-compliant/USB-2.0-certified
• Operates in both USB 2.0 high speed (HS), 480 Mbits/second, and full speed (FS), 12 Mbits/second
• Serial-to-parallel and parallel-to-serial conversions
• 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface
• Synchronous field and EOP detection on receive packets
• Synchronous field and EOP generation on transmit packets
• Data and clock recovery from the USB serial stream
• Bit stuffing/unstuffing; bit stuff error detection
• Staging register to manage data rate variation due to bit stuffing/unstuffing
• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface
• Ability to switch between FS and HS terminations and signaling
• Supports detection of USB reset, suspend, and resume
• Supports HS identification and detection as defined by the USB 2.0 Specification
• Supports transmission of resume signaling
• 3.3V operation
• Two package options—48-pin FBGA, and 56-pin SSOP
• All required terminations, including 1.5-K ohm pull-up on DPLUS, are internal to chip
• Supports USB 2.0 test modes.
XTALIN/
USB
OUT
EZ-USB TX2
OSC
XCVR
USB
2.0
Full-Speed Rx
High-Speed Rx
High-Speed Tx
Full-Speed Tx
PLL
20X
Features
Traffic
Sync
PLL_480
CY7C68000
Figure 1-1. Block Diagram
CY7C68000
Elasticity
Buffer
Digital
Digital
Fast
Fast
Rx
Tx
UTMI CLK
Digital
Digital
Rx
Tx
CY7C68000
UTMI Rx Data 8/16
UTMI Rx Ctl
UTMI Rx Data 8/16
UTMI Tx Ctl
UTMI CLK
Page 3 of 14
BIDI Option
Also