ADV7190KST Analog Devices Inc, ADV7190KST Datasheet - Page 20

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ADV7190KST

Manufacturer Part Number
ADV7190KST
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV7190KST

Number Of Dac's
6
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
LQFP
Pin Count
64
Lead Free Status / RoHS Status
Not Compliant

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ADV7190/ADV7191
When RESET is released Y, Cr, Cb values corresponding to a
black screen are input to the ADV7190/ADV7191. Output
timing signals are still suppressed at this stage. DACs A, B, C
are switched off and DACs D, E, F are switched on.
When the user requires valid data, Pixel Data Valid Control is
enabled (MR26 = 1) to allow the valid pixel data to pass through
the encoder. Digital output timing signals become active and the
encoder timing is now under the control of the Timing Registers.
If at this stage, the user wishes to select a different video standard
PIXEL_DATA_VALID
DIGITAL TIMING
RESET
DAC D,
DAC E
DAC A,
DAC B,
DAC C
DAC F
MR26
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
XXXXXXX
Figure 31. RESET Sequence Timing Diagram
XXXXXXX
XXXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
OFF
0
–20–
to that on the NTSC_PAL pin, Standard I
enabled (MR25 = 1) and the video standard required is selected
by programming Mode Register 0 (Output Video Standard
Selection). Figure 31 illustrates the RESET sequence timing.
BLACK VALUE WITH SYNC
BLACK VALUE
1
VALID VIDEO
VALID VIDEO
VALID VIDEO
TIMING ACTIVE
2
C Control should be
REV. B

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