ADV7190KST Analog Devices Inc, ADV7190KST Datasheet - Page 27

• Manufacturer Part Number: ADV7190KST
• Manufacturer: Analog Devices Inc

Specifications of ADV7190KST

• Number Of Dac's: 6
• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Not Compliant

MPU PORT DESCRIPTION
The ADV7190/ADV7191 supports a two-wire serial (I
compatible) microprocessor bus driving multiple peripherals.
Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry
information between any device connected to the bus. Each
slave device is recognized by a unique address. The ADV7190/
ADV7191 has four possible slave addresses for both read and
write operations. These are unique addresses for each device
and are illustrated in Figure 46 and Figure 47. The LSB sets
either a read or write operation. Logic Level 1 corresponds to a
read operation while Logic Level 0 corresponds to a write opera-
tion. A1 is set by setting the ALSB pin of the ADV7190/ADV7191
to Logic Level 0 or Logic Level 1.
To control the various devices on the bus the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
is where the device monitors the SDA and SCL lines waiting
for the start condition and the correct transmitted address. The
R/W bit determines the direction of the data.
REV. B
1
0
Figure 46b. Slave Address for ADV7191
Figure 46a. Slave Address for ADV7190
1
1
SEQUENCE
SEQUENCE
WRITE
READ
0
0
S SLAVE ADDR A(S)
S SLAVE ADDR A(S)
1
1
S = START BIT
P = STOP BIT
0
0
LSB = 0
1
1
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
SUB ADDR
ADDRESS
CONTROL
SETUP BY
ADDRESS
CONTROL
SETUP BY
SUB ADDR
Figure 48. Write and Read Sequences
ALSB
ALSB
A1
A1
READ/WRITE
READ/WRITE
0
1
0
1
CONTROL
CONTROL
A(S)
A(S) S SLAVE ADDR
X
X
WRITE
READ
WRITE
READ
2
C-
DATA
–27–
LSB = 1
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7190/ADV7191 acts as a standard slave device on
the bus. The data on the SDA pin is eight bits long supporting
the 7-bit addresses plus the R/W bit. It interprets the first byte as
the device address and the second byte as the starting subaddress.
The subaddresses autoincrement allowing data to be written to
or read from the starting subaddress. A data transfer is always
terminated by a stop condition. The user can also access any
unique subaddress register on a one-by-one basis without having
to update all the registers. There is one exception. The Subcarrier
Frequency Registers should be updated in sequence, starting
with Subcarrier Frequency Register 0. The autoincrement function
should be then used to increment and access Subcarrier Frequency
Registers 1, 2, and 3. The Subcarrier Frequency Registers should
not be accessed independently.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period the
user should issue only one start condition, one stop condition,
or a single stop condition followed by a single start condition.
If, an invalid subaddress is issued by the user, the ADV7190/
ADV7191 will not issue an acknowledge and will return to the
idle condition. If in autoincrement mode, the user exceeds the
highest subaddress, the following action will be taken:
1. In Read Mode, the highest subaddress register contents
2. In Write Mode, the data for the invalid byte will be not be
Figure 47 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 48 shows bus write and read sequences.
SCLOCK
A(S)
SDATA
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7190/ADV7191 and the part will return
to the idle condition.
A(S)
START ADDR R/W ACK SUBADDRESS ACK
S
DATA
1–7
Figure 47. Bus Data Transfer
DATA
A(M)
8
9
A(S) P
1–7
ADV7190/ADV7191
DATA
8
9
A(M)
1–7
DATA
P
8
ACK
9
STOP
P