ADV7170KS Analog Devices Inc, ADV7170KS Datasheet - Page 32

• Manufacturer Part Number: ADV7170KS
• Manufacturer: Analog Devices Inc

Specifications of ADV7170KS

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

ADV7170/ADV7171
Reserved (MR27)
A Logic Level 0 must be written to this bit.
MODE REGISTER 3 MR3 (MR37 TO MR30)
(Address [SR4 to SR0] = 03H)
Mode Register 3 is an 8-bit-wide register. Figure 41 shows the
various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION
Revision Code (MR30 to MR31)
These bits are read-only and indicate the revision of the device.
VBI Open (MR32)
This bit determines whether or not data in the vertical blanking
interval (VBI) is output to the analog outputs or blanked. VBI
data insertion is not available in Slave Mode 0. Also, when both
BLANK input control and VBI-open are enabled, BLANK input
control has priority; that is, VBI data insertion does not work.
Table 12. DAC Output Configuration Matrix
MR34
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CVBS:
Y:
C:
U:
V:
R:
G:
B:
Each DAC can be powered on or off individually with the following control bits (0 = ON; 1 = OFF):
MR13-DAC C
MR14-DAC D
MR15-DAC B
MR16-DAC A
Composite video baseband signal
Luminance component signal (for YUV or Y/C mode)
Chrominance signal (for Y/C mode)
Chrominance component signal (for YUV mode)
Chrominance component signal (for YUV mode)
RED Component video (for RGB mode)
GREEN Component video (for RGB mode)
BLUE Component video (for RGB mode)
MR40
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MR41
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
MR33
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC A
CVBS
Y
CVBS
Y
CVBS
G
CVBS
Y
C
Y
C
Y
C
G
C
Y
Rev. C | Page 32 of 64
DAC B
CVBS
CVBS
CVBS
CVBS
B
B
U
U
CVBS
CVBS
CVBS
CVBS
B
B
U
U
DAC Output (MR33)
This bit is used to switch the DAC outputs from SCART to a
EUROSCART configuration. A complete table of all DAC output
configurations is shown in Table 12.
Chroma Output Select (MR34)
With this active high bit it is possible to output YUV data with a
composite output on the fourth DAC or a chroma output on the
fourth DAC (0 = CVBS; 1 = CHROMA).
Teletext Enable (MR35)
This bit must be set to 1 to enable teletext data insertion on the
TTX pin.
TTXREQ Bit Mode Control (MR36)
This bit enables switching of the teletext request signal from a
continuous high signal (MR36 = 0) to a bit wise request signal
(MR36 = 1).
Input Default Color (MR37)
This bit determines the default output color from the DACs for
zero input pixel data (or disconnected). A Logic Level 0 means that
the color corresponding to 00000000 is displayed. A Logic Level 1
forces the output color to black for 00000000 pixel input video data.
DAC C
C
C
C
C
R
R
V
V
C
C
C
C
R
R
V
V
DAC D
Y
CVBS
Y
CVBS
G
CVBS
Y
CVBS
Y
C
Y
C
G
C
Y
C
Simultaneous Output
2 composite and Y/C
2 composite and Y/C
2 composite and Y/C
2 composite and Y/C
RGB and composite
RGB and composite
YUV and composite
YUV and composite
1 composite, Y and 2C
1 composite, Y and 2C
1 composite, Y and 2C
1 composite, Y and 2C
RGB and C
RGB and C
YUV and C
YUV and C