ADV7170KS Analog Devices Inc, ADV7170KS Datasheet - Page 43

• Manufacturer Part Number: ADV7170KS
• Manufacturer: Analog Devices Inc

Specifications of ADV7170KS

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

APPENDIX 5—TELETEXT INSERTION
The t
interpolate input data on TTX and insert it onto the CVBS
or Y outputs, such that it appears t
leading edge of the horizontal signal. Time TTX
pipeline delay time by the source that is gated by the TTXREQ
signal in order to deliver TTX data.
With the programmability offered with the TTXREQ signal on
the rising/falling edges, the TTX data is always inserted at the
correct position of 10.2 μs after the leading edge of horizontal
sync pulse, thus enabling a source interface with variable
pipeline delays.
The width of the TTXREQ signal must always be maintained to
allow the insertion of 360 (to comply with the Teletext Standard
of PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/sec;
this is achieved by setting TC03 to TC00 to 0. The insertion
window is not open if the teletext enable bit (MR35) is set to 0.
PD
is the time needed by the ADV7170/ADV7171 to
TTX
TTXREQ
CVBS/Y
HSYNC
DATA
t
t
TTX
SYNTTXOUT
PD
TELETEXT VBI LINE
= PIPELINE DELAY THROUGH ADV7170/ADV7171
DEL
t
PD
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
= 10.2μs
TTX
SYNTTXOUT
ST
10.2μs
t
SYNTTXOUT
= 10.2 μs after the
TTX
DEL
DEL
is the
Figure 60. Teletext Functionality Diagram
t
PD
Figure 59. Teletext VBI Line
Rev. C | Page 43 of 64
RUN-IN CLOCK
45 BYTES (360 BITS) – PAL
PROGRAMMABLE PULSE EDGES
ADDRESS AND DATA
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and
the system CLOCK (27 MHz) for 50 Hz is as follows:
Thus, 37 TTX bits correspond to 144 clocks (27 MHz), and
each bit has a width of nearly four clock cycles. The ADV7170/
ADV7171 use an internal sequencer and variable phase
interpolation filter to minimize the phase jitter and thus
generate a bandlimited signal that can be output on the CVBS
and Y outputs.
At the TTX input, the bit duration scheme repeats after every 37
TTX bits or 144 clock cycles. The protocol requires that TTX
Bit 10, Bit 19, Bit 28, and Bit 37 are carried by three clock cycles;
all other bits are carried by four clock cycles. After 37 TTX bits,
the next bits with three clock cycles are Bit 47, Bit 56, Bit 65,
and Bit 74. This scheme holds for all following cycles of 37 TTX
bits, until all 360 TTX bits are completed. All teletext lines are
implemented in the same way. Individual control of teletext
lines is controlled by teletext setup registers.
(27 MHz/4) = 6.75 MHz
(6.9375 × 10
6
/6.75 × 10
6
) = 1.027777
ADV7170/ADV7171