ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 103

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Table 105. 20-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 106. 20-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 107. 20-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 108. 30-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x10
0x18
0x01
0x6C
Setting
0x02
0x1C
0x10
0x10
0x1C
0x01
0x6C
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
0x6C
Setting
0x02
0x1C
0x10
0x1C
0x01
0x2C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Rev. A | Page 103 of 108
Table 109. 30-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 110. 30-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 111. 30-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 112. 30-Bit 625p RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
0x35
Setting
0x02
0x1C
0x10
0x18
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x1C
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
0x2C
Setting
0x02
0x1C
0x10
0x10
0x18
0x01
0x2C
0x02
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
RGB input enabled.
ADV7340/ADV7341