ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 53

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV7340/ADV7341 include two on-chip phase-locked
loops (PLLs) that allow for oversampling of SD, ED, and HD
video data. Table 41 shows the various oversampling rates
supported in the ADV7340/ADV7341.
SD Only, ED Only, and HD Only Modes
PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is
unused in these modes. PLL 1 is disabled by default and can be
enabled using Subaddress 0x00, Bit 1 = 0.
SD and ED/HD Simultaneous Modes
Both PLL 1 and PLL 2 are used in simultaneous modes. The use
of two PLLs allows for independent oversampling of SD and
ED/HD video. PLL 1 is used to oversample SD video data, and
PLL 2 is used to oversample ED/HD video data. In simultaneous
modes, PLL 2 is always enabled. PLL 1 is disabled by default and
can be enabled using Subaddress 0x00, Bit 1 = 0.
ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to the
standards available in the ED/HD standard table (Subad-
dress 0x30, Bits[7:3]), the ED/HD nonstandard timing mode
can be used to interface to the ADV7340/ADV7341. ED/HD
Table 41. Output Oversampling Modes and Rates
Input Mode
Subaddress 0x01 Bits[6:4]
000
000
001/010
001/010
001/010
001/010
011/100
011/100
011/100
011/100
111
111
Table 42. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition
b to c
c to a
a to b
c to b
1
2
a = trilevel synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level.
If P_VSYNC = 1, it should transition to 0. If P_VSYNC = 0, it should remain at 0. If trilevel synchronization pulse generation is not required, P_VSYNC should always be 0.
SD only
SD only
ED only
ED only
HD only
HD only
SD and ED
SD and ED
SD and HD
SD and HD
ED only (at 54 MHz)
ED only (at 54 MHz)
1
PLL and Oversampling Control
Subaddress 0x00, Bit 1
1
0
1
0
1
0
1
0
1
0
1
0
Rev. A | Page 53 of 108
P_HSYNC
1 to 0
0
0 to 1
0 to 1
nonstandard timing mode can be enabled by setting Subaddress
0x30, Bits[7:3] to 00001.
A clock signal must be provided on the CLKIN_A pin. P_HSYNC
and P_VSYNC must be toggled by the user to generate the
appropriate horizontal and vertical synchronization pulses on the
analog output from the encoder.
output levels that can be generated.
required to generate these output levels.
Embedded EAV/SAV timing codes are not supported in ED/HD
nonstandard timing mode.
The user must ensure that appropriate pixel data is applied to
the encoder where the blanking level is expected at the output.
Macrovision (ADV7340 only) and output oversampling are not
available in ED/HD nonstandard timing mode.
a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.
b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.
c = SYNCHRONIZATION PULSE LEVEL.
ANA
OUTPUT
b
LOG
Figure 59. ED/HD Nonstandard Timing Mode Output Levels
c
a
Oversampling Mode and Rate
SD (2×)
SD (16×)
ED (1×)
ED (8×)
HD (1×)
HD (4×)
SD (2×) and ED (8×)
SD (16×) and ED (8×)
SD (2×) and HD (4×)
SD (16×) and HD (4×)
ED only (at 54 MHz) (1×)
ED only (at 54 MHz) (8×)
BLANKING LEVEL
b
Figure 59
P_VSYNC
1 to 0 or 0
0 to 1
1
0
ADV7340/ADV7341
Table 42
illustrates the various
2
ACTIVE VIDEO
lists the transitions
b