AD73411BBZ-80 Analog Devices Inc, AD73411BBZ-80 Datasheet - Page 25

• Manufacturer Part Number: AD73411BBZ-80
• Manufacturer: Analog Devices Inc

Specifications of AD73411BBZ-80

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Compliant

Because the AD73411 includes an on-chip oscillator circuit, an
external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 14. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
CONTROLLER
INTERFACE
SYSTEM
1/2x CLOCK
1/2x CLOCK
SECTION
SECTION
SECTION
SECTION
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
AFE*
AFE*
AFE*
AFE*
OR
OR
OR
OR
OR
OR
16
HOST MEMORY MODE
CLKIN
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
CLKIN
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE C/PF2
MODE B/PF1
MODE A/PF0
IAD15-0
FULL MEMORY MODE
XTAL
FL0–2
PF3
XTAL
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IDMA PORT
SPORT1
SPORT0
SPORT1
SPORT0
CLKIN
AD73411
AD73411
DSP
ADDR13–0
DATA23–8
DATA23–0
PWDACK
PWDACK
IOMS
IOMS
XTAL
PWD
PWD
BMS
DMS
CMS
BMS
DMS
CMS
PMS
BGH
PMS
BGH
WR
RD
WR
BR
BG
BR
BG
RD
A0
14
1
24
16
*AFE SECTION CAN BE
CONNECTED TO EITHER
SPORT0 OR SPORT1
CLKOUT
D
A
23–16
D
A
D
A
D
13–0
23–0
10–0
23–8
13–0
15–8
ADDR
ADDR
A0–A21
DATA
CS
DATA
DATA
CS
(PERIPHERALS)
PM SEGMENTS
DM SEGMENTS
I/O SPACE
LOCATIONS
MEMORY
OVERLAY
MEMORY
TWO 8K
TWO 8K
BYTE
2048
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
Reset
The RESET signal initiates a master reset of the DSP section of
the AD73411. The RESET signal must be asserted during the
power-up sequence to assure proper initialization. RESET during
initial power-up must be held long enough to allow the internal
clock to stabilize. If RESET is activated any time after power-up,
the clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
to the processor, and for the internal phase-locked loop (PLL)
to lock onto the specific crystal frequency. A minimum of 2000
CLKIN cycles ensures that the PLL has locked, but does not
include the crystal oscillator start-up time. During this power-up
sequence the RESET signal should be held low. On any subse-
quent resets, the RESET signal must meet the minimum pulsewidth
specification, t
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and clears the MSTAT register.
When RESET is released, if there is no pending bus request and
the chip is configured for booting, the boot-loading sequence is
performed. Once boot loading completes, the first instruction is
fetched from on-chip program memory location 0x0000.
MODES OF OPERATION
Table XVII summarizes the AD73411 memory modes.
Setting Memory Mode
Memory Mode selection for the AD73411 is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order
of 100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the
pull-up or pull-down will hold the pin in a known state and will
not switch.
Active Configuration involves the use of a three-statable
external driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such
that it only drives the PF2 pin when RESET is active (low).
When RESET is deasserted, the driver should three-state, thus
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure the
programmable flag as an output when connected to a three-stated
buffer. This ensures that the pin will be held at a constant level
and not oscillate should the three-state driver’s level hover around
the logic switching point.
RSP
.
AD73411
DD
is applied