AD73411BB-40 Analog Devices Inc, AD73411BB-40 Datasheet - Page 27

• Manufacturer Part Number: AD73411BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73411BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table XX.
DMOVLAY Memory
0
1
2
I/O Space (Full Memory Mode)
The AD73411 supports an additional external memory space
called I/O space. This space is designed to support simple connec-
tions to peripherals (such as data converters and external registers)
or to bus interface ASIC data registers. I/O space supports 2048
locations of 16-bit-wide data. The lower 11-bits of the external
address bus are used; the upper three bits are undefined. Two
instructions were added to the core ADSP-2100 Family Instruc-
tion Set to read from and write to I/O memory space. The I/O
space also has four dedicated 3-bit wait state registers, IOWAIT0-
3, that specify up to seven wait states to be automatically generated
for each of four regions. The wait states act on address ranges as
shown in Table XXI.
Composite Memory Select (CMS)
The AD73411 has a programmable memory select signal that is
useful for generating memory select signals for memories mapped
to more than one space. The CMS signal is generated to have
the same timing as each of the individual memory select signals
(PMS, DMS, BMS, IOMS) but can combine their functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both program
and data memory, set the PMS and DMS bits in the CMSSEL
register and use the CMS pin to drive the chip select of the
memory; use either DMS or PMS as the additional address bit.
INTERNAL
MEMORY
EXTERNAL
MEMORY
Address Range Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
ACCESSIBLE WHEN
0x2000 – 0x3FFF
DMOVLAY = 0
DATA MEMORY
ACCESSIBLE
AT ADDRESS
Internal
External
Overlay 1
External
Overlay 2
ALWAYS
ACCESSIBLE WHEN
DMOVLAY = 1
Table XX. DMOVLAY Bits
ACCESSIBLE WHEN
DMOVLAY = 2
Table XXI. Wait States
0x0000–
0x1FFF
A13
Not Applicable Not Applicable
0
1
0x0000–
0x1FFF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
0x0000–
0x1FFF
DATA MEMORY
DMOVLAY = 1, 2
EXTERNAL 8K
32 MEMORY
8K INTERNAL
DMOVLAY = 0
REGISTERS
INTERNAL
MAPPED
WORDS
8160
A12:0
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
OR
ADDRESS
0 x 3FFF
0x3FE0
0x3FDF
0x1FFF
0x2000
0 x 0000
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset,
except the BMS bit.
Boot Memory Select (BMS) Disable
The AD73411 also lets you boot the processor from one exter-
nal memory space while using a different external memory space
for BDMA transfers during normal operation. You can use the
CMS to select the first external memory space for BDMA trans-
fers and BMS to select the second external memory space for
booting. The BMS signal can be disabled by setting Bit 3 of the
System Control Register to 1. The System Control Register is
illustrated in Figure 17.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Regis-
ter is shown in Figure 18. The byte memory space consists of
256 pages, each of which is 16K × 8.
The byte memory space on the AD73411 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16-, or 24-bit word transferred.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table XXII shows the data formats sup-
ported by the BDMA circuit.
SPORT0 ENABLE
SPORT1 ENABLE
SPORT1 CONFIGURE
1 = ENABLED
0 = DISABLED
1 = ENABLED
0 = DISABLED
1 = SERIAL PORT
0 = FI, FO, IRQ0,
15 14 13 12 11 10 9
IRQ1, SCLK
0
15 14 13 12 11 10 9
0
0
0
0
BMPAGE
0
0
0
0
SYSTEM CONTROL REGISTER
0
0
1
BDMA CONTROL
0
0
8
0
8
0
7
0
7
0
6
0
6
0
5
0
5
0
4
0
4
0
3
1
3
0
2
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
2
1
BTYPE
1
0
BDIR
AD73411
0 = LOAD FROM BM
1 = STORE TO BM
1
1
0
0
PWAIT
PROGRAM MEMORY
WAIT STATES
BMS ENABLE
0
1
0 = ENABLED
1 = DISABLED
DM (0x3FE3)
DM (0x3FFF)