AD73411BB-40 Analog Devices Inc, AD73411BB-40 Datasheet - Page 28

• Manufacturer Part Number: AD73411BB-40
• Manufacturer: Analog Devices Inc

Specifications of AD73411BB-40

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Package Type: BGA
• Lead Free Status / RoHS Status: Not Compliant

AD73411
BTYPE
00
01
10
11
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the
14-bit BWCOUNT register specifies the number of DSP words
to transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to exter-
nal memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the AD73411. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch the DMA starting
address (IDMAA) into the DSP’s IDMA control registers.
IAD[15] must be set = 0.
Internal
Memory Space
Program Memory
Data Memory
Data Memory
Data Memory
Table XXII. Data Formats
Word Size
24
16
8
8
Alignment
Full Word
Full Word
MSBs
LSBs
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
5. Host checks IACK line to see if the DSP has completed the
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
AD73411 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the AD73411’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the AD73411 that a particular trans-
action is required. In either case, there is a one-processor-cycle
delay for synchronization. The memory access consumes one
additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) di-
rects the AD73411 to write the address onto the IAD0–14 bus
into the IDMA Control Register. The IDMAA register, shown
below, is memory mapped at address DM (0x3FE0). Note that
the latched address (IDMAA) cannot be read back by the
host. See Figure 19 for more information on IDMA and DMA
memory maps.
Bootstrap Loading (Booting)
The AD73411 has two mechanisms to allow automatic loading
of the internal program memory after reset. The method for
booting after reset is controlled by the Mode A, B and C con-
figuration bits.
When the mode pins specify BDMA booting, the AD73411
initiates a BDMA boot sequence when reset is released.
nal memory (PM or DM).
previous IDMA operation.
15 14 13 12 11 10 9
U
IDMAD
DESTINATION MEMORY TYPE:
IDMA CONTROL (U = UNDEFINED AT RESET)
U
0 = PM
1 = DM
U
U
U
U
IDMAA ADDRESS
U
8
U
7
6
U
5
U
4
U
3
U
2
U
1
U
0
U
DM(0x3FE0)