MC34910G5AC Freescale, MC34910G5AC Datasheet - Page 42

• Manufacturer Part Number: MC34910G5AC
• Manufacturer: Freescale

Specifications of MC34910G5AC

• Turn Off Delay Time: 10us
• Number Of Drivers: 2
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

High Side Control Register - HSCR
Writing to this register returns the High Side Status Register
(HSSR).
PWMHSx - PWM Input Control Enable.
to control the respective high side switch. The corresponding
high side switch must be enabled (HSx bit).
HSx - HSx Switch Control.
high side switch.
High Side Status Register - HSSR
and is also returned when writing to the HSCR.
High Side thermal shutdown
setting all HSxOP and HSxCL bits simultaneously.
HSxOP - High Side Switch Open-Load Detection
conducting current below a certain threshold indicating
possible load disconnection.
HSxCL - High Side Current Limitation
switch is operating in current limitation mode.
42
33910
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
Table 19. High Side Control Register - $6
Condition
This register controls the operation of the high side drivers.
This write-only bit enables/disables the PWMIN input pin
1 = PWMIN input controls HSx output.
0 = HSx is controlled only by SPI.
This write-only bit enables/disables the corresponding
1 = HSx switch on.
0 = HSx switch off.
This register returns the status of the high side switches
A thermal shutdown of the high side drivers is indicated by
This read-only bit signals that the high side switches are
1 = HSx Open Load detected (or thermal shutdown)
0 = Normal
This read-only bit indicates that the respective high side
1 = HSx in current limitation (or thermal shutdown)
Reset
Reset
Value
Write
Table 20. High Side Status Register - $6/$7
Read
PWMHS2
C3
0
HS2OP
POR
S3
PWMHS1
C2
0
HS2CL
S2
POR, Reset mode, ext_reset, HSx
over-temp or (VSOV & HVSE)
HS2
HS1OP
C1
0
S1
HS1CL
S0
HS1
C0
0
Timing Control Register - TIMCR
sense and Forced Wake-up periods. Writing to the Timing
Control Register (TIMCR) will also return the Watchdog
Status Register (WDSR).
CS/WD - Cyclic Sense or Watchdog prescaler select
to, the Cyclic Sense/Forced Wake-up prescaler or the
Watchdog prescaler.
WDx - Watchdog Prescaler
prescaler and therefore selects the watchdog period in
accordance with
windowing watchdog is active.
Table 22. Watchdog Prescaler
CYSTx - Cyclic Sense Period Prescaler Select
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 44).
enabled when entering in Stop or Sleep mode. Otherwise, a
timed wake-up is performed after the period shown in
Table
WD2
0 = Normal
This register allows to configure the watchdog, the cyclic
This write-only bit selects which prescaler is being written
1 = Cyclic Sense/Forced Wake-up Prescaler selected
0 = Watchdog Prescaler select
This write-only bits selects the divider for the watchdog
This write-only bits selects the interval for the wake-up
This option is only active if one of the high side switches is
Table 21. Timing Control Register - $A
0
0
0
0
1
1
1
1
Condition
Reset
Value
Reset
23.
Write
WD1
0
0
1
1
0
0
1
1
CS/WD
Table
C3
-
-
WD0
Analog Integrated Circuit Device Data
0
1
0
1
0
1
0
1
22. This configuration is valid only if
CYST2
WD2
C2
0
Freescale Semiconductor
Prescaler Divider
CYST1
WD1
POR
C1
0
10
12
14
1
2
4
6
8
CYST0
WD0
C0
0